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@ -74,7 +74,7 @@
@@ -74,7 +74,7 @@
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// the 2nd bank of flash needs to be handled differently
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#define STM32_FLASH_BANK2_START (STM32_FLASH_BASE+0x00080000) |
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#if defined(STM32F4) |
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#if BOARD_FLASH_SIZE == 512 |
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#define STM32_FLASH_NPAGES 7 |
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static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(16), KB(16), KB(16), KB(16), KB(64), |
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@ -91,6 +91,24 @@ static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(16), KB(16), KB(16
@@ -91,6 +91,24 @@ static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(16), KB(16), KB(16
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KB(128), KB(128), KB(128), KB(128), KB(128), KB(128), KB(128), |
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KB(16), KB(16), KB(16), KB(16), KB(64), |
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KB(128), KB(128), KB(128), KB(128), KB(128), KB(128), KB(128)}; |
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#else |
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#error "BOARD_FLASH_SIZE invalid" |
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#endif |
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#elif defined(STM32F7) |
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#if BOARD_FLASH_SIZE == 1024 |
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#define STM32_FLASH_NPAGES 5 |
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static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(32), KB(32), KB(32), KB(128), KB(256) }; |
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#elif BOARD_FLASH_SIZE == 2048 |
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#define STM32_FLASH_NPAGES 9 |
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static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(32), KB(32), KB(32), KB(128), KB(256), |
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KB(256), KB(256), KB(256), KB(256) }; |
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#else |
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#error "BOARD_FLASH_SIZE invalid" |
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#endif |
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#else |
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#error "Unsupported processor for flash.c" |
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#endif |
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// keep a cache of the page addresses
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@ -134,8 +152,10 @@ static void stm32_flash_unlock(void)
@@ -134,8 +152,10 @@ static void stm32_flash_unlock(void)
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FLASH->KEYR = FLASH_KEY2; |
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} |
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#ifdef FLASH_ACR_DCEN |
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// disable the data cache - see stm32 errata 2.1.11
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FLASH->ACR &= ~FLASH_ACR_DCEN; |
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#endif |
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} |
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void stm32_flash_lock(void) |
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@ -143,10 +163,12 @@ void stm32_flash_lock(void)
@@ -143,10 +163,12 @@ void stm32_flash_lock(void)
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stm32_flash_wait_idle(); |
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FLASH->CR |= FLASH_CR_LOCK; |
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#ifdef FLASH_ACR_DCEN |
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// reset and re-enable the data cache - see stm32 errata 2.1.11
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FLASH->ACR |= FLASH_ACR_DCRST; |
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FLASH->ACR &= ~FLASH_ACR_DCRST; |
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FLASH->ACR |= FLASH_ACR_DCEN; |
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#endif |
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} |
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