Andrew Tridgell
6 years ago
3 changed files with 843 additions and 349 deletions
@ -0,0 +1,384 @@
@@ -0,0 +1,384 @@
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio |
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License"); |
||||
you may not use this file except in compliance with the License. |
||||
You may obtain a copy of the License at |
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software |
||||
distributed under the License is distributed on an "AS IS" BASIS, |
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
See the License for the specific language governing permissions and |
||||
limitations under the License. |
||||
*/ |
||||
/*
|
||||
* This file is free software: you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation, either version 3 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, but |
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
||||
* See the GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License along |
||||
* with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Modified for use in AP_HAL by Andrew Tridgell and Siddharth Bharat Purohit |
||||
*/ |
||||
/*
|
||||
this provides the default mcuconf.h for each board. Override values in hwdef.dat |
||||
*/ |
||||
#pragma once |
||||
|
||||
|
||||
/*
|
||||
* STM32F4xx drivers configuration. |
||||
* The following settings override the default settings present in |
||||
* the various device driver implementation headers. |
||||
* Note that the settings for each driver only have effect if the whole |
||||
* driver is enabled in halconf.h. |
||||
* |
||||
* IRQ priorities: |
||||
* 15...0 Lowest...Highest. |
||||
* |
||||
* DMA priorities: |
||||
* 0...3 Lowest...Highest. |
||||
*/ |
||||
|
||||
/*
|
||||
* HAL driver system settings. |
||||
*/ |
||||
#define STM32_NO_INIT FALSE |
||||
|
||||
#ifndef STM32_HSI_ENABLED |
||||
#define STM32_HSI_ENABLED TRUE |
||||
#endif |
||||
|
||||
#ifndef STM32_LSI_ENABLED |
||||
#define STM32_LSI_ENABLED TRUE |
||||
#endif |
||||
|
||||
#ifndef STM32_HSE_ENABLED |
||||
#define STM32_HSE_ENABLED TRUE |
||||
#endif |
||||
|
||||
#ifndef STM32_LSE_ENABLED |
||||
#define STM32_LSE_ENABLED FALSE |
||||
#endif |
||||
|
||||
#ifndef STM32_CLOCK48_REQUIRED |
||||
#define STM32_CLOCK48_REQUIRED TRUE |
||||
#endif |
||||
|
||||
#ifndef STM32_SW |
||||
#define STM32_SW STM32_SW_PLL |
||||
#endif |
||||
|
||||
#ifndef STM32_PLLSRC |
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE |
||||
#endif |
||||
#ifndef STM32_PLLM_VALUE |
||||
#define STM32_PLLM_VALUE 24 |
||||
#endif |
||||
#ifndef STM32_PLLN_VALUE |
||||
#define STM32_PLLN_VALUE 336 |
||||
#endif |
||||
#ifndef STM32_PLLP_VALUE |
||||
#define STM32_PLLP_VALUE 2 |
||||
#endif |
||||
#ifndef STM32_PLLQ_VALUE |
||||
#define STM32_PLLQ_VALUE 7 |
||||
#endif |
||||
|
||||
#define STM32_HPRE STM32_HPRE_DIV1 |
||||
#define STM32_PPRE1 STM32_PPRE1_DIV4 |
||||
#define STM32_PPRE2 STM32_PPRE2_DIV2 |
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI |
||||
#define STM32_RTCPRE_VALUE 8 |
||||
#define STM32_MCO1SEL STM32_MCO1SEL_HSI |
||||
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 |
||||
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK |
||||
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 |
||||
#define STM32_I2SSRC STM32_I2SSRC_CKIN |
||||
#define STM32_PLLI2SN_VALUE 192 |
||||
#define STM32_PLLI2SR_VALUE 5 |
||||
#define STM32_PVD_ENABLE FALSE |
||||
#define STM32_PLS STM32_PLS_LEV0 |
||||
#define STM32_BKPRAM_ENABLE FALSE |
||||
|
||||
/*
|
||||
* ADC driver system settings. |
||||
*/ |
||||
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 |
||||
#define STM32_ADC_USE_ADC1 TRUE |
||||
#define STM32_ADC_USE_ADC2 FALSE |
||||
#define STM32_ADC_USE_ADC3 FALSE |
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2 |
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2 |
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2 |
||||
#define STM32_ADC_IRQ_PRIORITY 6 |
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 |
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 |
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 |
||||
|
||||
/*
|
||||
* CAN driver system settings. |
||||
*/ |
||||
#define STM32_CAN_USE_CAN1 FALSE |
||||
#define STM32_CAN_USE_CAN2 FALSE |
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 11 |
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY 11 |
||||
|
||||
/*
|
||||
* DAC driver system settings. |
||||
*/ |
||||
#define STM32_DAC_DUAL_MODE FALSE |
||||
#define STM32_DAC_USE_DAC1_CH1 FALSE |
||||
#define STM32_DAC_USE_DAC1_CH2 FALSE |
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 |
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 |
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 |
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 |
||||
|
||||
/*
|
||||
* EXT driver system settings. |
||||
*/ |
||||
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 |
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 |
||||
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 |
||||
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 |
||||
|
||||
/*
|
||||
* GPT driver system settings. |
||||
*/ |
||||
#ifndef STM32_GPT_USE_TIM1 |
||||
#define STM32_GPT_USE_TIM1 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM2 |
||||
#define STM32_GPT_USE_TIM2 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM3 |
||||
#define STM32_GPT_USE_TIM3 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM4 |
||||
#define STM32_GPT_USE_TIM4 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM5 |
||||
#define STM32_GPT_USE_TIM5 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM6 |
||||
#define STM32_GPT_USE_TIM6 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM7 |
||||
#define STM32_GPT_USE_TIM7 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM8 |
||||
#define STM32_GPT_USE_TIM8 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM9 |
||||
#define STM32_GPT_USE_TIM9 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM10 |
||||
#define STM32_GPT_USE_TIM10 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM11 |
||||
#define STM32_GPT_USE_TIM11 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM12 |
||||
#define STM32_GPT_USE_TIM12 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM13 |
||||
#define STM32_GPT_USE_TIM13 FALSE |
||||
#endif |
||||
#ifndef STM32_GPT_USE_TIM14 |
||||
#define STM32_GPT_USE_TIM14 FALSE |
||||
#endif |
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM5_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM6_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM7_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM8_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM9_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM11_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM12_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM14_IRQ_PRIORITY 7 |
||||
|
||||
/*
|
||||
* I2C driver system settings. |
||||
*/ |
||||
#define STM32_I2C_BUSY_TIMEOUT 50 |
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 5 |
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 5 |
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY 5 |
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3 |
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3 |
||||
#define STM32_I2C_I2C3_DMA_PRIORITY 3 |
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") |
||||
|
||||
/*
|
||||
* I2S driver system settings. |
||||
*/ |
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY 10 |
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY 10 |
||||
#define STM32_I2S_SPI2_DMA_PRIORITY 1 |
||||
#define STM32_I2S_SPI3_DMA_PRIORITY 1 |
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") |
||||
|
||||
/*
|
||||
* ICU driver system settings. |
||||
*/ |
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM9_IRQ_PRIORITY 7 |
||||
|
||||
/*
|
||||
* EICU driver system settings. |
||||
*/ |
||||
#define STM32_EICU_TIM1_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM2_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM3_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM4_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM5_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM8_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM9_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM10_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM11_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM12_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM13_IRQ_PRIORITY 6 |
||||
#define STM32_EICU_TIM14_IRQ_PRIORITY 6 |
||||
|
||||
/*
|
||||
* MAC driver system settings. |
||||
*/ |
||||
#define STM32_MAC_TRANSMIT_BUFFERS 2 |
||||
#define STM32_MAC_RECEIVE_BUFFERS 4 |
||||
#define STM32_MAC_BUFFERS_SIZE 1522 |
||||
#define STM32_MAC_PHY_TIMEOUT 100 |
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE |
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY 13 |
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 |
||||
|
||||
/*
|
||||
* PWM driver system settings. |
||||
*/ |
||||
#ifndef STM32_PWM_USE_ADVANCED |
||||
#define STM32_PWM_USE_ADVANCED FALSE |
||||
#endif |
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM9_IRQ_PRIORITY 7 |
||||
|
||||
/*
|
||||
* SDC driver system settings. |
||||
*/ |
||||
#define STM32_SDC_SDIO_DMA_PRIORITY 3 |
||||
#define STM32_SDC_SDIO_IRQ_PRIORITY 9 |
||||
#define STM32_SDC_WRITE_TIMEOUT_MS 1000 |
||||
#define STM32_SDC_READ_TIMEOUT_MS 1000 |
||||
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 |
||||
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE |
||||
|
||||
/*
|
||||
* SERIAL driver system settings. |
||||
*/ |
||||
#define STM32_SERIAL_USART1_PRIORITY 11 |
||||
#define STM32_SERIAL_USART2_PRIORITY 11 |
||||
#define STM32_SERIAL_USART3_PRIORITY 11 |
||||
#define STM32_SERIAL_UART4_PRIORITY 11 |
||||
#define STM32_SERIAL_UART5_PRIORITY 11 |
||||
#define STM32_SERIAL_USART6_PRIORITY 11 |
||||
#define STM32_SERIAL_UART7_PRIORITY 11 |
||||
#define STM32_SERIAL_UART8_PRIORITY 11 |
||||
|
||||
/*
|
||||
* SPI driver system settings. |
||||
*/ |
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI4_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
||||
|
||||
/*
|
||||
* ST driver system settings. |
||||
*/ |
||||
#define STM32_ST_IRQ_PRIORITY 8 |
||||
#ifndef STM32_ST_USE_TIMER |
||||
#define STM32_ST_USE_TIMER 2 |
||||
#endif |
||||
|
||||
/*
|
||||
* UART driver system settings. |
||||
*/ |
||||
#define STM32_UART_USART1_IRQ_PRIORITY 12 |
||||
#define STM32_UART_USART2_IRQ_PRIORITY 12 |
||||
#define STM32_UART_USART3_IRQ_PRIORITY 12 |
||||
#define STM32_UART_UART4_IRQ_PRIORITY 12 |
||||
#define STM32_UART_UART5_IRQ_PRIORITY 12 |
||||
#define STM32_UART_USART6_IRQ_PRIORITY 12 |
||||
#define STM32_UART_USART1_DMA_PRIORITY 0 |
||||
#define STM32_UART_USART2_DMA_PRIORITY 0 |
||||
#define STM32_UART_USART3_DMA_PRIORITY 0 |
||||
#define STM32_UART_UART4_DMA_PRIORITY 0 |
||||
#define STM32_UART_UART5_DMA_PRIORITY 0 |
||||
#define STM32_UART_USART6_DMA_PRIORITY 0 |
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") |
||||
|
||||
/*
|
||||
* USB driver system settings. |
||||
*/ |
||||
#ifndef STM32_USB_OTG1_IRQ_PRIORITY |
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14 |
||||
#endif |
||||
#ifndef STM32_USB_OTG2_IRQ_PRIORITY |
||||
#define STM32_USB_OTG2_IRQ_PRIORITY 14 |
||||
#endif |
||||
#ifndef STM32_USB_OTG1_RX_FIFO_SIZE |
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512 |
||||
#endif |
||||
#ifndef STM32_USB_OTG2_RX_FIFO_SIZE |
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 |
||||
#endif |
||||
#ifndef STM32_USB_OTG_THREAD_PRIO |
||||
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO |
||||
#endif |
||||
#ifndef STM32_USB_OTG_THREAD_STACK_SIZE |
||||
#define STM32_USB_OTG_THREAD_STACK_SIZE 128 |
||||
#endif |
||||
#ifndef STM32_USB_OTGFIFO_FILL_BASEPRI |
||||
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 |
||||
#endif |
||||
|
||||
/*
|
||||
* WDG driver system settings. |
||||
*/ |
||||
#define STM32_WDG_USE_IWDG FALSE |
||||
@ -0,0 +1,452 @@
@@ -0,0 +1,452 @@
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio |
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License"); |
||||
you may not use this file except in compliance with the License. |
||||
You may obtain a copy of the License at |
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software |
||||
distributed under the License is distributed on an "AS IS" BASIS, |
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
See the License for the specific language governing permissions and |
||||
limitations under the License. |
||||
*/ |
||||
/*
|
||||
this header is modelled on the one for the Nucleo-144 H743 board from ChibiOS |
||||
*/ |
||||
#pragma once |
||||
|
||||
/*
|
||||
* General settings. |
||||
*/ |
||||
#define STM32_NO_INIT FALSE |
||||
#define STM32_SYS_CK_ENFORCED_VALUE STM32_HSICLK |
||||
|
||||
/*
|
||||
* Memory attributes settings. |
||||
*/ |
||||
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE |
||||
#define STM32_NOCACHE_SRAM3 TRUE |
||||
|
||||
/*
|
||||
* PWR system settings. |
||||
* Reading STM32 Reference Manual is required. |
||||
* Register constants are taken from the ST header. |
||||
*/ |
||||
#define STM32_VOS STM32_VOS_SCALE1 |
||||
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) |
||||
#define STM32_PWR_CR2 (PWR_CR2_BREN) |
||||
#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN) |
||||
#define STM32_PWR_CPUCR 0 |
||||
|
||||
/*
|
||||
* Clock tree static settings. |
||||
* Reading STM32 Reference Manual is required. |
||||
*/ |
||||
#define STM32_HSI_ENABLED TRUE |
||||
#define STM32_LSI_ENABLED TRUE |
||||
#define STM32_CSI_ENABLED TRUE |
||||
#define STM32_HSI48_ENABLED TRUE |
||||
#define STM32_HSE_ENABLED TRUE |
||||
#define STM32_LSE_ENABLED TRUE |
||||
#define STM32_HSIDIV STM32_HSIDIV_DIV1 |
||||
|
||||
/*
|
||||
* PLLs static settings. |
||||
* Reading STM32 Reference Manual is required. |
||||
*/ |
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE_CK |
||||
#define STM32_PLLCFGR_MASK ~0 |
||||
#define STM32_PLL1_ENABLED TRUE |
||||
#define STM32_PLL1_P_ENABLED TRUE |
||||
#define STM32_PLL1_Q_ENABLED TRUE |
||||
#define STM32_PLL1_R_ENABLED TRUE |
||||
#ifndef STM32_PLL1_DIVM_VALUE |
||||
#define STM32_PLL1_DIVM_VALUE 4 |
||||
#endif |
||||
#define STM32_PLL1_DIVN_VALUE 400 |
||||
#define STM32_PLL1_FRACN_VALUE 0 |
||||
#define STM32_PLL1_DIVP_VALUE 2 |
||||
#define STM32_PLL1_DIVQ_VALUE 4 |
||||
#define STM32_PLL1_DIVR_VALUE 2 |
||||
#define STM32_PLL2_ENABLED TRUE |
||||
#define STM32_PLL2_P_ENABLED TRUE |
||||
#define STM32_PLL2_Q_ENABLED TRUE |
||||
#define STM32_PLL2_R_ENABLED TRUE |
||||
#ifndef STM32_PLL2_DIVM_VALUE |
||||
#define STM32_PLL2_DIVM_VALUE 4 |
||||
#endif |
||||
#define STM32_PLL2_DIVN_VALUE 400 |
||||
#define STM32_PLL2_FRACN_VALUE 0 |
||||
#define STM32_PLL2_DIVP_VALUE 40 |
||||
#define STM32_PLL2_DIVQ_VALUE 8 |
||||
#define STM32_PLL2_DIVR_VALUE 8 |
||||
#define STM32_PLL3_ENABLED TRUE |
||||
#define STM32_PLL3_P_ENABLED TRUE |
||||
#define STM32_PLL3_Q_ENABLED TRUE |
||||
#define STM32_PLL3_R_ENABLED TRUE |
||||
#ifndef STM32_PLL3_DIVM_VALUE |
||||
#define STM32_PLL3_DIVM_VALUE 8 |
||||
#endif |
||||
#define STM32_PLL3_DIVN_VALUE 336 |
||||
#define STM32_PLL3_FRACN_VALUE 0 |
||||
#define STM32_PLL3_DIVP_VALUE 2 |
||||
#define STM32_PLL3_DIVQ_VALUE 7 |
||||
#define STM32_PLL3_DIVR_VALUE 2 |
||||
|
||||
/*
|
||||
* Core clocks dynamic settings (can be changed at runtime). |
||||
* Reading STM32 Reference Manual is required. |
||||
*/ |
||||
#define STM32_SW STM32_SW_PLL1_P_CK |
||||
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK |
||||
#define STM32_D1CPRE STM32_D1CPRE_DIV1 |
||||
#define STM32_D1HPRE STM32_D1HPRE_DIV2 |
||||
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2 |
||||
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2 |
||||
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2 |
||||
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2 |
||||
|
||||
/*
|
||||
* Peripherals clocks static settings. |
||||
* Reading STM32 Reference Manual is required. |
||||
*/ |
||||
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK |
||||
#define STM32_MCO1PRE_VALUE 4 |
||||
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK |
||||
#define STM32_MCO2PRE_VALUE 4 |
||||
#define STM32_TIMPRE_ENABLE TRUE |
||||
#define STM32_HRTIMSEL 0 |
||||
#define STM32_STOPKERWUCK 0 |
||||
#define STM32_STOPWUCK 0 |
||||
#define STM32_RTCPRE_VALUE 8 |
||||
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK |
||||
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK |
||||
#define STM32_QSPISEL STM32_QSPISEL_HCLK |
||||
#define STM32_FMCSEL STM32_QSPISEL_HCLK |
||||
#define STM32_SWPSEL STM32_SWPSEL_PCLK1 |
||||
#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK |
||||
#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 |
||||
#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK |
||||
#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2 |
||||
#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK |
||||
#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK |
||||
#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK |
||||
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 |
||||
#define STM32_CECSEL STM32_CECSEL_LSE_CK |
||||
#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK |
||||
#define STM32_I2C123SEL STM32_I2C123SEL_PCLK1 |
||||
#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK |
||||
#define STM32_USART16SEL STM32_USART16SEL_PCLK2 |
||||
#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1 |
||||
#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4 |
||||
#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK |
||||
#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK |
||||
#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK |
||||
#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4 |
||||
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4 |
||||
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4 |
||||
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4 |
||||
|
||||
/*
|
||||
* IRQ system settings. |
||||
*/ |
||||
#define STM32_IRQ_EXTI0_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI1_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI2_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI3_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI4_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI5_9_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI10_15_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI16_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI17_PRIORITY 15 |
||||
#define STM32_IRQ_EXTI18_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI19_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI20_PRIORITY 6 |
||||
#define STM32_IRQ_EXTI21_PRIORITY 15 |
||||
#define STM32_IRQ_EXTI22_PRIORITY 15 |
||||
|
||||
/*
|
||||
* ADC driver system settings. |
||||
*/ |
||||
#define STM32_ADC_DUAL_MODE FALSE |
||||
#define STM32_ADC_COMPACT_SAMPLES FALSE |
||||
#define STM32_ADC_USE_ADC12 TRUE |
||||
#define STM32_ADC_USE_ADC3 FALSE |
||||
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY |
||||
#define STM32_ADC_ADC12_DMA_PRIORITY 2 |
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2 |
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY 5 |
||||
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 |
||||
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 |
||||
|
||||
/*
|
||||
* CAN driver system settings. |
||||
*/ |
||||
#define STM32_CAN_USE_CAN1 FALSE |
||||
#define STM32_CAN_USE_CAN2 FALSE |
||||
#define STM32_CAN_USE_CAN3 FALSE |
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 11 |
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY 11 |
||||
#define STM32_CAN_CAN3_IRQ_PRIORITY 11 |
||||
|
||||
/*
|
||||
* DAC driver system settings. |
||||
*/ |
||||
#define STM32_DAC_DUAL_MODE FALSE |
||||
#define STM32_DAC_USE_DAC1_CH1 FALSE |
||||
#define STM32_DAC_USE_DAC1_CH2 FALSE |
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 |
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 |
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 |
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 |
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
|
||||
/*
|
||||
* GPT driver system settings. |
||||
*/ |
||||
#define STM32_GPT_USE_TIM1 FALSE |
||||
#define STM32_GPT_USE_TIM2 FALSE |
||||
#define STM32_GPT_USE_TIM3 FALSE |
||||
#define STM32_GPT_USE_TIM4 FALSE |
||||
#define STM32_GPT_USE_TIM5 FALSE |
||||
#define STM32_GPT_USE_TIM6 FALSE |
||||
#define STM32_GPT_USE_TIM7 FALSE |
||||
#define STM32_GPT_USE_TIM8 FALSE |
||||
#define STM32_GPT_USE_TIM9 FALSE |
||||
#define STM32_GPT_USE_TIM11 FALSE |
||||
#define STM32_GPT_USE_TIM12 FALSE |
||||
#define STM32_GPT_USE_TIM14 FALSE |
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM5_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM6_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM7_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM8_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM9_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM11_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM12_IRQ_PRIORITY 7 |
||||
#define STM32_GPT_TIM14_IRQ_PRIORITY 7 |
||||
|
||||
/*
|
||||
* I2C driver system settings. |
||||
*/ |
||||
#define STM32_I2C_USE_I2C1 FALSE |
||||
#define STM32_I2C_USE_I2C2 FALSE |
||||
#define STM32_I2C_USE_I2C3 FALSE |
||||
#define STM32_I2C_USE_I2C4 FALSE |
||||
#define STM32_I2C_BUSY_TIMEOUT 50 |
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY |
||||
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY |
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 5 |
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 5 |
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY 5 |
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY 5 |
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3 |
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3 |
||||
#define STM32_I2C_I2C3_DMA_PRIORITY 3 |
||||
#define STM32_I2C_I2C4_DMA_PRIORITY 3 |
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") |
||||
|
||||
/*
|
||||
* ICU driver system settings. |
||||
*/ |
||||
#define STM32_ICU_USE_TIM1 FALSE |
||||
#define STM32_ICU_USE_TIM2 FALSE |
||||
#define STM32_ICU_USE_TIM3 FALSE |
||||
#define STM32_ICU_USE_TIM4 FALSE |
||||
#define STM32_ICU_USE_TIM5 FALSE |
||||
#define STM32_ICU_USE_TIM8 FALSE |
||||
#define STM32_ICU_USE_TIM9 FALSE |
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 |
||||
#define STM32_ICU_TIM9_IRQ_PRIORITY 7 |
||||
|
||||
/*
|
||||
* MAC driver system settings. |
||||
*/ |
||||
#define STM32_MAC_TRANSMIT_BUFFERS 2 |
||||
#define STM32_MAC_RECEIVE_BUFFERS 4 |
||||
#define STM32_MAC_BUFFERS_SIZE 1522 |
||||
#define STM32_MAC_PHY_TIMEOUT 100 |
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE |
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY 13 |
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 |
||||
|
||||
/*
|
||||
* PWM driver system settings. |
||||
*/ |
||||
#define STM32_PWM_USE_ADVANCED FALSE |
||||
#define STM32_PWM_USE_TIM1 FALSE |
||||
#define STM32_PWM_USE_TIM2 FALSE |
||||
#define STM32_PWM_USE_TIM3 FALSE |
||||
#define STM32_PWM_USE_TIM4 FALSE |
||||
#define STM32_PWM_USE_TIM5 FALSE |
||||
#define STM32_PWM_USE_TIM8 FALSE |
||||
#define STM32_PWM_USE_TIM9 FALSE |
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY 7 |
||||
#define STM32_PWM_TIM9_IRQ_PRIORITY 7 |
||||
|
||||
/*
|
||||
* RTC driver system settings. |
||||
*/ |
||||
#define STM32_RTC_PRESA_VALUE 32 |
||||
#define STM32_RTC_PRESS_VALUE 1024 |
||||
#define STM32_RTC_CR_INIT 0 |
||||
#define STM32_RTC_TAMPCR_INIT 0 |
||||
|
||||
/*
|
||||
* SDC driver system settings. |
||||
*/ |
||||
#define STM32_SDC_USE_SDMMC1 FALSE |
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE |
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 |
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 |
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY 10 |
||||
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 |
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 |
||||
|
||||
/*
|
||||
* SERIAL driver system settings. |
||||
*/ |
||||
#define STM32_SERIAL_USE_USART1 FALSE |
||||
#define STM32_SERIAL_USE_USART2 FALSE |
||||
#define STM32_SERIAL_USE_USART3 TRUE |
||||
#define STM32_SERIAL_USE_UART4 FALSE |
||||
#define STM32_SERIAL_USE_UART5 FALSE |
||||
#define STM32_SERIAL_USE_USART6 FALSE |
||||
#define STM32_SERIAL_USE_UART7 FALSE |
||||
#define STM32_SERIAL_USE_UART8 FALSE |
||||
#define STM32_SERIAL_USART1_PRIORITY 12 |
||||
#define STM32_SERIAL_USART2_PRIORITY 12 |
||||
#define STM32_SERIAL_USART3_PRIORITY 12 |
||||
#define STM32_SERIAL_UART4_PRIORITY 12 |
||||
#define STM32_SERIAL_UART5_PRIORITY 12 |
||||
#define STM32_SERIAL_USART6_PRIORITY 12 |
||||
#define STM32_SERIAL_UART7_PRIORITY 12 |
||||
#define STM32_SERIAL_UART8_PRIORITY 12 |
||||
|
||||
/*
|
||||
* SPI driver system settings. |
||||
*/ |
||||
#define STM32_SPI_USE_SPI1 TRUE |
||||
#define STM32_SPI_USE_SPI2 FALSE |
||||
#define STM32_SPI_USE_SPI3 FALSE |
||||
#define STM32_SPI_USE_SPI4 FALSE |
||||
#define STM32_SPI_USE_SPI5 FALSE |
||||
#define STM32_SPI_USE_SPI6 FALSE |
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY |
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI4_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI5_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI6_DMA_PRIORITY 1 |
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_SPI6_IRQ_PRIORITY 10 |
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
||||
|
||||
/*
|
||||
* ST driver system settings. |
||||
*/ |
||||
#define STM32_ST_IRQ_PRIORITY 8 |
||||
#define STM32_ST_USE_TIMER 2 |
||||
|
||||
/*
|
||||
* UART driver system settings. |
||||
*/ |
||||
#define STM32_UART_USE_USART1 FALSE |
||||
#define STM32_UART_USE_USART2 FALSE |
||||
#define STM32_UART_USE_USART3 FALSE |
||||
#define STM32_UART_USE_UART4 FALSE |
||||
#define STM32_UART_USE_UART5 FALSE |
||||
#define STM32_UART_USE_USART6 FALSE |
||||
#define STM32_UART_USE_UART7 FALSE |
||||
#define STM32_UART_USE_UART8 FALSE |
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
||||
#define STM32_UART_USART1_IRQ_PRIORITY 12 |
||||
#define STM32_UART_USART2_IRQ_PRIORITY 12 |
||||
#define STM32_UART_USART3_IRQ_PRIORITY 12 |
||||
#define STM32_UART_UART4_IRQ_PRIORITY 12 |
||||
#define STM32_UART_UART5_IRQ_PRIORITY 12 |
||||
#define STM32_UART_USART6_IRQ_PRIORITY 12 |
||||
#define STM32_UART_USART1_DMA_PRIORITY 0 |
||||
#define STM32_UART_USART2_DMA_PRIORITY 0 |
||||
#define STM32_UART_USART3_DMA_PRIORITY 0 |
||||
#define STM32_UART_UART4_DMA_PRIORITY 0 |
||||
#define STM32_UART_UART5_DMA_PRIORITY 0 |
||||
#define STM32_UART_USART6_DMA_PRIORITY 0 |
||||
#define STM32_UART_UART7_DMA_PRIORITY 0 |
||||
#define STM32_UART_UART8_DMA_PRIORITY 0 |
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") |
||||
|
||||
/*
|
||||
* USB driver system settings. |
||||
*/ |
||||
#define STM32_USB_USE_OTG1 TRUE |
||||
#define STM32_USB_USE_OTG2 TRUE |
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14 |
||||
#define STM32_USB_OTG2_IRQ_PRIORITY 14 |
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512 |
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 |
||||
#define STM32_USB_HOST_WAKEUP_DURATION 2 |
||||
|
||||
/*
|
||||
* WDG driver system settings. |
||||
*/ |
||||
#define STM32_WDG_USE_IWDG FALSE |
||||
|
||||
#define STM32_EXTI_ENHANCED |
||||
Loading…
Reference in new issue