From 6a0c46d241de14dd2d3e1e13aa005e333b7ee198 Mon Sep 17 00:00:00 2001
From: bugobliterator <siddharthbharatpurohit@gmail.com>
Date: Tue, 8 Mar 2022 17:32:47 +0530
Subject: [PATCH] AP_HAL_Periph: assert clock is FDCANCLK is 80MHz for H7
 boards

---
 libraries/AP_HAL_ChibiOS/CANFDIface.cpp | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/libraries/AP_HAL_ChibiOS/CANFDIface.cpp b/libraries/AP_HAL_ChibiOS/CANFDIface.cpp
index b84173b82b..f7330c9a83 100644
--- a/libraries/AP_HAL_ChibiOS/CANFDIface.cpp
+++ b/libraries/AP_HAL_ChibiOS/CANFDIface.cpp
@@ -87,7 +87,13 @@
 
 extern AP_HAL::HAL& hal;
 
-static_assert(STM32_FDCANCLK <= 80U*1000U*1000U, "FDCAN clock must be max 80MHz");
+#define STR(x) #x
+#define XSTR(x) STR(x)
+#if defined(STM32H7)
+static_assert(STM32_FDCANCLK == 80U*1000U*1000U, "FDCAN clock must be 80MHz, got " XSTR(STM32_FDCANCLK));
+#else
+static_assert(STM32_FDCANCLK <= 80U*1000U*1000U, "FDCAN clock must be max 80MHz, got " XSTR(STM32_FDCANCLK));
+#endif
 
 using namespace ChibiOS;