Eugene Shamaev
8 years ago
committed by
Francisco Ferreira
7 changed files with 1755 additions and 41 deletions
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/*
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* Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com> |
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* |
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* With modifications for Ardupilot CAN driver |
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* Copyright (C) 2017 Eugene Shamaev |
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*/ |
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#pragma once |
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#include "AP_HAL_PX4.h" |
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#include <systemlib/perf_counter.h> |
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#include <AP_HAL/CAN.h> |
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#include <pthread.h> |
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#include <semaphore.h> |
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#include "bxcan.h" |
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#include "AP_HAL/utility/RingBuffer.h" |
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#if defined(GPIO_CAN2_RX) && defined(GPIO_CAN2_TX) |
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#define CAN_STM32_NUM_IFACES 2 |
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#else |
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#define CAN_STM32_NUM_IFACES 1 |
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#endif |
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#define CAN_STM32_RX_QUEUE_SIZE 64 |
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namespace PX4 { |
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/**
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* Driver error codes. |
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* These values can be returned from driver functions negated. |
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*/ |
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static const int16_t ErrUnknown = 1000; ///< Reserved for future use
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static const int16_t ErrNotImplemented = 1001; ///< Feature not implemented
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static const int16_t ErrInvalidBitRate = 1002; ///< Bit rate not supported
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static const int16_t ErrLogic = 1003; ///< Internal logic error
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static const int16_t ErrUnsupportedFrame = 1004; ///< Frame not supported (e.g. RTR, CAN FD, etc)
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static const int16_t ErrMsrInakNotSet = 1005; ///< INAK bit of the MSR register is not 1
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static const int16_t ErrMsrInakNotCleared = 1006; ///< INAK bit of the MSR register is not 0
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static const int16_t ErrBitRateNotDetected = 1007; ///< Auto bit rate detection could not be finished
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/**
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* RX queue item. |
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* The application shall not use this directly. |
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*/ |
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struct CanRxItem { |
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uint64_t utc_usec; |
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uavcan::CanFrame frame; |
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uavcan::CanIOFlags flags; |
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CanRxItem() : |
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utc_usec(0), flags(0) |
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{ |
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} |
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}; |
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struct CriticalSectionLocker { |
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const irqstate_t flags_; |
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CriticalSectionLocker() : |
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flags_(irqsave()) |
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{ |
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} |
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~CriticalSectionLocker() |
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{ |
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irqrestore(flags_); |
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} |
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}; |
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namespace clock { |
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uint64_t getUtcUSecFromCanInterrupt(); |
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uavcan::MonotonicTime getMonotonic(); |
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} |
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class BusEvent: uavcan::Noncopyable { |
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public: |
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BusEvent(PX4CANManager& can_driver); |
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~BusEvent(); |
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bool wait(uavcan::MonotonicDuration duration); |
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static void signalFromCallOut(BusEvent *sem); |
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void signalFromInterrupt(); |
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sem_t _wait_semaphore; |
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volatile uint16_t _signal; |
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}; |
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class PX4CAN: public AP_HAL::CAN { |
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struct Timings { |
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uint16_t prescaler; |
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uint8_t sjw; |
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uint8_t bs1; |
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uint8_t bs2; |
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Timings() : |
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prescaler(0), sjw(0), bs1(0), bs2(0) |
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{ |
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} |
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}; |
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struct TxItem { |
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uavcan::MonotonicTime deadline; |
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uavcan::CanFrame frame; |
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bool pending; |
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bool loopback; |
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bool abort_on_error; |
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TxItem() : |
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pending(false), loopback(false), abort_on_error(false) |
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{ |
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} |
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}; |
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enum { |
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NumTxMailboxes = 3 |
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}; |
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enum { |
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NumFilters = 28 |
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}; |
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static const uint32_t TSR_ABRQx[NumTxMailboxes]; |
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ObjectBuffer<CanRxItem> rx_queue_; |
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bxcan::CanType* const can_; |
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uint64_t error_cnt_; |
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uint32_t served_aborts_cnt_; |
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BusEvent& update_event_; |
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TxItem pending_tx_[NumTxMailboxes]; |
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uint8_t peak_tx_mailbox_index_; |
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const uint8_t self_index_; |
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bool had_activity_; |
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uint32_t bitrate_; |
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int computeTimings(uint32_t target_bitrate, Timings& out_timings); |
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virtual int16_t send(const uavcan::CanFrame& frame, uavcan::MonotonicTime tx_deadline, |
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uavcan::CanIOFlags flags) override; |
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virtual int16_t receive(uavcan::CanFrame& out_frame, uavcan::MonotonicTime& out_ts_monotonic, |
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uavcan::UtcTime& out_ts_utc, uavcan::CanIOFlags& out_flags) override; |
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virtual int16_t configureFilters(const uavcan::CanFilterConfig* filter_configs, uint16_t num_configs) override; |
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virtual uint16_t getNumFilters() const override |
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{ |
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return NumFilters; |
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} |
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void handleTxMailboxInterrupt(uint8_t mailbox_index, bool txok, uint64_t utc_usec); |
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bool waitMsrINakBitStateChange(bool target_state); |
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bool initialized_; |
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public: |
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enum { |
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MaxRxQueueCapacity = 254 |
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}; |
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enum OperatingMode { |
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NormalMode, SilentMode |
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}; |
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PX4CAN(bxcan::CanType* can, BusEvent& update_event, uint8_t self_index, uint8_t rx_queue_capacity) : |
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rx_queue_(rx_queue_capacity), can_(can), error_cnt_(0), served_aborts_cnt_(0), update_event_( |
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update_event), peak_tx_mailbox_index_(0), self_index_(self_index), had_activity_(false), bitrate_( |
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0), initialized_(false) |
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{ |
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UAVCAN_ASSERT(self_index_ < CAN_STM32_NUM_IFACES); |
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} |
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/**
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* Initializes the hardware CAN controller. |
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* Assumes: |
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* - Iface clock is enabled |
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* - Iface has been resetted via RCC |
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* - Caller will configure NVIC by itself |
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*/ |
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int init(const uint32_t bitrate, const OperatingMode mode); |
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void handleTxInterrupt(uint64_t utc_usec); |
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void handleRxInterrupt(uint8_t fifo_index, uint64_t utc_usec); |
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/**
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* This method is used to count errors and abort transmission on error if necessary. |
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* This functionality used to be implemented in the SCE interrupt handler, but that approach was |
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* generating too much processing overhead, especially on disconnected interfaces. |
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* |
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* Should be called from RX ISR, TX ISR, and select(); interrupts must be enabled. |
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*/ |
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void pollErrorFlagsFromISR(); |
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void discardTimedOutTxMailboxes(uavcan::MonotonicTime current_time); |
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bool canAcceptNewTxFrame(const uavcan::CanFrame& frame) const; |
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bool isRxBufferEmpty() const; |
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/**
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* Total number of hardware failures and other kinds of errors (e.g. queue overruns). |
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* May increase continuously if the interface is not connected to the bus. |
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*/ |
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virtual uint64_t getErrorCount() const override; |
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/**
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* Number of times the driver exercised library's requirement to abort transmission on first error. |
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* This is an atomic read, it doesn't require a critical section. |
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* See @ref uavcan::CanIOFlagAbortOnError. |
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*/ |
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uint32_t getVoluntaryTxAbortCount() const |
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{ |
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return served_aborts_cnt_; |
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} |
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/**
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* Returns the number of frames pending in the RX queue. |
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* This is intended for debug use only. |
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*/ |
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unsigned getRxQueueLength() const; |
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/**
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* Whether this iface had at least one successful IO since the previous call of this method. |
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* This is designed for use with iface activity LEDs. |
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*/ |
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bool hadActivity(); |
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/**
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* Peak number of TX mailboxes used concurrently since initialization. |
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* Range is [1, 3]. |
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* Value of 3 suggests that priority inversion could be taking place. |
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*/ |
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uint8_t getPeakNumTxMailboxesUsed() const |
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{ |
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return uint8_t(peak_tx_mailbox_index_ + 1); |
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} |
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bool begin(uint32_t bitrate) override; |
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void end() override |
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{ |
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} |
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void reset() override; |
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int32_t tx_pending() override; |
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int32_t available() override; |
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bool is_initialized() override; |
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}; |
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class PX4CANManager: public AP_HAL::CANManager { |
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BusEvent update_event_; |
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PX4CAN if0_; |
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PX4CAN if1_; |
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uint8_t can_number_; |
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virtual int16_t select(uavcan::CanSelectMasks& inout_masks, |
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const uavcan::CanFrame* (&pending_tx)[uavcan::MaxCanIfaces], uavcan::MonotonicTime blocking_deadline) override; |
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static void initOnce(uint8_t can_number); |
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bool initialized_; |
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static PX4CAN* ifaces[CAN_STM32_NUM_IFACES]; |
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public: |
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PX4CANManager() : |
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update_event_(*this), if0_(bxcan::Can[0], update_event_, 0, CAN_STM32_RX_QUEUE_SIZE), if1_( |
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bxcan::Can[1], update_event_, 1, CAN_STM32_RX_QUEUE_SIZE), can_number_(0), initialized_( |
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false), p_uavcan(nullptr) |
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{ |
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uavcan::StaticAssert<(CAN_STM32_RX_QUEUE_SIZE <= PX4CAN::MaxRxQueueCapacity)>::check(); |
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} |
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/**
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* This function returns select masks indicating which interfaces are available for read/write. |
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*/ |
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uavcan::CanSelectMasks makeSelectMasks(const uavcan::CanFrame* (&pending_tx)[uavcan::MaxCanIfaces]) const; |
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/**
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* Whether there's at least one interface where receive() would return a frame. |
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*/ |
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bool hasReadableInterfaces() const; |
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/**
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* Returns zero if OK. |
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* Returns negative value if failed (e.g. invalid bitrate). |
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*/ |
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int init(const uint32_t bitrate, const PX4CAN::OperatingMode mode, uint8_t can_number); |
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virtual PX4CAN* getIface(uint8_t iface_index) override; |
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virtual uint8_t getNumIfaces() const override |
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{ |
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if (can_number_ >= 2) { |
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return CAN_STM32_NUM_IFACES; |
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} |
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return 1; |
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} |
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/**
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* Whether at least one iface had at least one successful IO since previous call of this method. |
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* This is designed for use with iface activity LEDs. |
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*/ |
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bool hadActivity(); |
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bool begin(uint32_t bitrate, uint8_t can_number) override; |
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bool is_initialized() override; |
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AP_UAVCAN *p_uavcan; |
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AP_UAVCAN *get_UAVCAN(void) override; |
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void set_UAVCAN(AP_UAVCAN *uavcan) override; |
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}; |
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} |
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@ -0,0 +1,294 @@
@@ -0,0 +1,294 @@
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/*
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* Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com> |
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* Bit definitions were copied from NuttX STM32 CAN driver. |
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* |
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* With modifications for Ardupilot CAN driver |
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* Copyright (C) 2017 Eugene Shamaev |
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*/ |
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#pragma once |
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#include <uavcan/uavcan.hpp> |
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#include <stdint.h> |
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#include <nuttx/arch.h> |
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#include <arch/board/board.h> |
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#include <chip/stm32_tim.h> |
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#include <syslog.h> |
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#include <nuttx/config.h> |
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#include <nuttx/fs/fs.h> |
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#include <nuttx/irq.h> |
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#include <nuttx/mm.h> |
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#include <pthread.h> |
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#ifndef UAVCAN_CPP_VERSION |
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# error UAVCAN_CPP_VERSION |
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#endif |
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#if UAVCAN_CPP_VERSION < UAVCAN_CPP11 |
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// #undef'ed at the end of this file
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# define constexpr const |
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#endif |
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namespace PX4 { |
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namespace bxcan { |
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# define CAN_IRQ_ATTACH(irq, handler) \ |
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do { \
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const int res = irq_attach(irq, handler); \
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(void)res; \
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assert(res >= 0); \
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up_enable_irq(irq); \
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} while(0) |
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struct TxMailboxType { |
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volatile uint32_t TIR; |
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volatile uint32_t TDTR; |
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volatile uint32_t TDLR; |
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volatile uint32_t TDHR; |
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}; |
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struct RxMailboxType { |
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volatile uint32_t RIR; |
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volatile uint32_t RDTR; |
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volatile uint32_t RDLR; |
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volatile uint32_t RDHR; |
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}; |
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struct FilterRegisterType { |
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volatile uint32_t FR1; |
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volatile uint32_t FR2; |
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}; |
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struct CanType { |
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volatile uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
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volatile uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
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volatile uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
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volatile uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
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volatile uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
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volatile uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
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volatile uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
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volatile uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
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uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
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TxMailboxType TxMailbox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
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RxMailboxType RxMailbox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
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uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
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volatile uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
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volatile uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
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uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
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volatile uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
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uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
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volatile uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
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uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
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volatile uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
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uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
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FilterRegisterType FilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
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}; |
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/**
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* CANx register sets |
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*/ |
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CanType* const Can[2] = { reinterpret_cast<CanType*>(STM32_CAN1_BASE), reinterpret_cast<CanType*>(STM32_CAN2_BASE) }; |
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/* CAN master control register */ |
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constexpr unsigned long MCR_INRQ = (1U << 0); /* Bit 0: Initialization Request */ |
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constexpr unsigned long MCR_SLEEP = (1U << 1); /* Bit 1: Sleep Mode Request */ |
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constexpr unsigned long MCR_TXFP = (1U << 2); /* Bit 2: Transmit FIFO Priority */ |
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constexpr unsigned long MCR_RFLM = (1U << 3); /* Bit 3: Receive FIFO Locked Mode */ |
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constexpr unsigned long MCR_NART = (1U << 4); /* Bit 4: No Automatic Retransmission */ |
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constexpr unsigned long MCR_AWUM = (1U << 5); /* Bit 5: Automatic Wakeup Mode */ |
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constexpr unsigned long MCR_ABOM = (1U << 6); /* Bit 6: Automatic Bus-Off Management */ |
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constexpr unsigned long MCR_TTCM = (1U << 7); /* Bit 7: Time Triggered Communication Mode Enable */ |
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constexpr unsigned long MCR_RESET = (1U << 15);/* Bit 15: bxCAN software master reset */ |
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constexpr unsigned long MCR_DBF = (1U << 16);/* Bit 16: Debug freeze */ |
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/* CAN master status register */ |
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constexpr unsigned long MSR_INAK = (1U << 0); /* Bit 0: Initialization Acknowledge */ |
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constexpr unsigned long MSR_SLAK = (1U << 1); /* Bit 1: Sleep Acknowledge */ |
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constexpr unsigned long MSR_ERRI = (1U << 2); /* Bit 2: Error Interrupt */ |
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constexpr unsigned long MSR_WKUI = (1U << 3); /* Bit 3: Wakeup Interrupt */ |
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constexpr unsigned long MSR_SLAKI = (1U << 4); /* Bit 4: Sleep acknowledge interrupt */ |
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constexpr unsigned long MSR_TXM = (1U << 8); /* Bit 8: Transmit Mode */ |
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constexpr unsigned long MSR_RXM = (1U << 9); /* Bit 9: Receive Mode */ |
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constexpr unsigned long MSR_SAMP = (1U << 10);/* Bit 10: Last Sample Point */ |
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constexpr unsigned long MSR_RX = (1U << 11);/* Bit 11: CAN Rx Signal */ |
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/* CAN transmit status register */ |
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constexpr unsigned long TSR_RQCP0 = (1U << 0); /* Bit 0: Request Completed Mailbox 0 */ |
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constexpr unsigned long TSR_TXOK0 = (1U << 1); /* Bit 1 : Transmission OK of Mailbox 0 */ |
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constexpr unsigned long TSR_ALST0 = (1U << 2); /* Bit 2 : Arbitration Lost for Mailbox 0 */ |
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constexpr unsigned long TSR_TERR0 = (1U << 3); /* Bit 3 : Transmission Error of Mailbox 0 */ |
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constexpr unsigned long TSR_ABRQ0 = (1U << 7); /* Bit 7 : Abort Request for Mailbox 0 */ |
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constexpr unsigned long TSR_RQCP1 = (1U << 8); /* Bit 8 : Request Completed Mailbox 1 */ |
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constexpr unsigned long TSR_TXOK1 = (1U << 9); /* Bit 9 : Transmission OK of Mailbox 1 */ |
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constexpr unsigned long TSR_ALST1 = (1U << 10);/* Bit 10 : Arbitration Lost for Mailbox 1 */ |
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constexpr unsigned long TSR_TERR1 = (1U << 11);/* Bit 11 : Transmission Error of Mailbox 1 */ |
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constexpr unsigned long TSR_ABRQ1 = (1U << 15);/* Bit 15 : Abort Request for Mailbox 1 */ |
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constexpr unsigned long TSR_RQCP2 = (1U << 16);/* Bit 16 : Request Completed Mailbox 2 */ |
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constexpr unsigned long TSR_TXOK2 = (1U << 17);/* Bit 17 : Transmission OK of Mailbox 2 */ |
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constexpr unsigned long TSR_ALST2 = (1U << 18);/* Bit 18: Arbitration Lost for Mailbox 2 */ |
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constexpr unsigned long TSR_TERR2 = (1U << 19);/* Bit 19: Transmission Error of Mailbox 2 */ |
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constexpr unsigned long TSR_ABRQ2 = (1U << 23);/* Bit 23: Abort Request for Mailbox 2 */ |
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constexpr unsigned long TSR_CODE_SHIFT = (24U); /* Bits 25-24: Mailbox Code */ |
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constexpr unsigned long TSR_CODE_MASK = (3U << TSR_CODE_SHIFT); |
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constexpr unsigned long TSR_TME0 = (1U << 26);/* Bit 26: Transmit Mailbox 0 Empty */ |
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constexpr unsigned long TSR_TME1 = (1U << 27);/* Bit 27: Transmit Mailbox 1 Empty */ |
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constexpr unsigned long TSR_TME2 = (1U << 28);/* Bit 28: Transmit Mailbox 2 Empty */ |
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constexpr unsigned long TSR_LOW0 = (1U << 29);/* Bit 29: Lowest Priority Flag for Mailbox 0 */ |
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constexpr unsigned long TSR_LOW1 = (1U << 30);/* Bit 30: Lowest Priority Flag for Mailbox 1 */ |
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constexpr unsigned long TSR_LOW2 = (1U << 31);/* Bit 31: Lowest Priority Flag for Mailbox 2 */ |
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/* CAN receive FIFO 0/1 registers */ |
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constexpr unsigned long RFR_FMP_SHIFT = (0U); /* Bits 1-0: FIFO Message Pending */ |
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constexpr unsigned long RFR_FMP_MASK = (3U << RFR_FMP_SHIFT); |
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constexpr unsigned long RFR_FULL = (1U << 3); /* Bit 3: FIFO 0 Full */ |
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constexpr unsigned long RFR_FOVR = (1U << 4); /* Bit 4: FIFO 0 Overrun */ |
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constexpr unsigned long RFR_RFOM = (1U << 5); /* Bit 5: Release FIFO 0 Output Mailbox */ |
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/* CAN interrupt enable register */ |
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constexpr unsigned long IER_TMEIE = (1U << 0); /* Bit 0: Transmit Mailbox Empty Interrupt Enable */ |
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constexpr unsigned long IER_FMPIE0 = (1U << 1); /* Bit 1: FIFO Message Pending Interrupt Enable */ |
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constexpr unsigned long IER_FFIE0 = (1U << 2); /* Bit 2: FIFO Full Interrupt Enable */ |
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constexpr unsigned long IER_FOVIE0 = (1U << 3); /* Bit 3: FIFO Overrun Interrupt Enable */ |
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constexpr unsigned long IER_FMPIE1 = (1U << 4); /* Bit 4: FIFO Message Pending Interrupt Enable */ |
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constexpr unsigned long IER_FFIE1 = (1U << 5); /* Bit 5: FIFO Full Interrupt Enable */ |
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constexpr unsigned long IER_FOVIE1 = (1U << 6); /* Bit 6: FIFO Overrun Interrupt Enable */ |
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constexpr unsigned long IER_EWGIE = (1U << 8); /* Bit 8: Error Warning Interrupt Enable */ |
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constexpr unsigned long IER_EPVIE = (1U << 9); /* Bit 9: Error Passive Interrupt Enable */ |
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constexpr unsigned long IER_BOFIE = (1U << 10);/* Bit 10: Bus-Off Interrupt Enable */ |
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constexpr unsigned long IER_LECIE = (1U << 11);/* Bit 11: Last Error Code Interrupt Enable */ |
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constexpr unsigned long IER_ERRIE = (1U << 15);/* Bit 15: Error Interrupt Enable */ |
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constexpr unsigned long IER_WKUIE = (1U << 16);/* Bit 16: Wakeup Interrupt Enable */ |
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constexpr unsigned long IER_SLKIE = (1U << 17);/* Bit 17: Sleep Interrupt Enable */ |
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|
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/* CAN error status register */ |
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|
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constexpr unsigned long ESR_EWGF = (1U << 0); /* Bit 0: Error Warning Flag */ |
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constexpr unsigned long ESR_EPVF = (1U << 1); /* Bit 1: Error Passive Flag */ |
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constexpr unsigned long ESR_BOFF = (1U << 2); /* Bit 2: Bus-Off Flag */ |
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constexpr unsigned long ESR_LEC_SHIFT = (4U); /* Bits 6-4: Last Error Code */ |
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constexpr unsigned long ESR_LEC_MASK = (7U << ESR_LEC_SHIFT); |
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constexpr unsigned long ESR_NOERROR = (0U << ESR_LEC_SHIFT);/* 000: No Error */ |
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constexpr unsigned long ESR_STUFFERROR = (1U << ESR_LEC_SHIFT);/* 001: Stuff Error */ |
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constexpr unsigned long ESR_FORMERROR = (2U << ESR_LEC_SHIFT);/* 010: Form Error */ |
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constexpr unsigned long ESR_ACKERROR = (3U << ESR_LEC_SHIFT);/* 011: Acknowledgment Error */ |
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constexpr unsigned long ESR_BRECERROR = (4U << ESR_LEC_SHIFT);/* 100: Bit recessive Error */ |
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constexpr unsigned long ESR_BDOMERROR = (5U << ESR_LEC_SHIFT);/* 101: Bit dominant Error */ |
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constexpr unsigned long ESR_CRCERRPR = (6U << ESR_LEC_SHIFT);/* 110: CRC Error */ |
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constexpr unsigned long ESR_SWERROR = (7U << ESR_LEC_SHIFT);/* 111: Set by software */ |
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constexpr unsigned long ESR_TEC_SHIFT = (16U); /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ |
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constexpr unsigned long ESR_TEC_MASK = (0xFFU << ESR_TEC_SHIFT); |
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constexpr unsigned long ESR_REC_SHIFT = (24U); /* Bits 31-24: Receive Error Counter */ |
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constexpr unsigned long ESR_REC_MASK = (0xFFU << ESR_REC_SHIFT); |
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|
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/* CAN bit timing register */ |
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|
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constexpr unsigned long BTR_BRP_SHIFT = (0U); /* Bits 9-0: Baud Rate Prescaler */ |
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constexpr unsigned long BTR_BRP_MASK = (0x03FFU << BTR_BRP_SHIFT); |
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constexpr unsigned long BTR_TS1_SHIFT = (16U); /* Bits 19-16: Time Segment 1 */ |
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constexpr unsigned long BTR_TS1_MASK = (0x0FU << BTR_TS1_SHIFT); |
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constexpr unsigned long BTR_TS2_SHIFT = (20U); /* Bits 22-20: Time Segment 2 */ |
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constexpr unsigned long BTR_TS2_MASK = (7U << BTR_TS2_SHIFT); |
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constexpr unsigned long BTR_SJW_SHIFT = (24U); /* Bits 25-24: Resynchronization Jump Width */ |
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constexpr unsigned long BTR_SJW_MASK = (3U << BTR_SJW_SHIFT); |
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constexpr unsigned long BTR_LBKM = (1U << 30);/* Bit 30: Loop Back Mode (Debug);*/ |
||||
constexpr unsigned long BTR_SILM = (1U << 31);/* Bit 31: Silent Mode (Debug);*/ |
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|
||||
constexpr unsigned long BTR_BRP_MAX = (1024U); /* Maximum BTR value (without decrement);*/ |
||||
constexpr unsigned long BTR_TSEG1_MAX = (16U); /* Maximum TSEG1 value (without decrement);*/ |
||||
constexpr unsigned long BTR_TSEG2_MAX = (8U); /* Maximum TSEG2 value (without decrement);*/ |
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|
||||
/* TX mailbox identifier register */ |
||||
|
||||
constexpr unsigned long TIR_TXRQ = (1U << 0); /* Bit 0: Transmit Mailbox Request */ |
||||
constexpr unsigned long TIR_RTR = (1U << 1); /* Bit 1: Remote Transmission Request */ |
||||
constexpr unsigned long TIR_IDE = (1U << 2); /* Bit 2: Identifier Extension */ |
||||
constexpr unsigned long TIR_EXID_SHIFT = (3U); /* Bit 3-31: Extended Identifier */ |
||||
constexpr unsigned long TIR_EXID_MASK = (0x1FFFFFFFU << TIR_EXID_SHIFT); |
||||
constexpr unsigned long TIR_STID_SHIFT = (21U); /* Bits 21-31: Standard Identifier */ |
||||
constexpr unsigned long TIR_STID_MASK = (0x07FFU << TIR_STID_SHIFT); |
||||
|
||||
/* Mailbox data length control and time stamp register */ |
||||
|
||||
constexpr unsigned long TDTR_DLC_SHIFT = (0U); /* Bits 3:0: Data Length Code */ |
||||
constexpr unsigned long TDTR_DLC_MASK = (0x0FU << TDTR_DLC_SHIFT); |
||||
constexpr unsigned long TDTR_TGT = (1U << 8); /* Bit 8: Transmit Global Time */ |
||||
constexpr unsigned long TDTR_TIME_SHIFT = (16U); /* Bits 31:16: Message Time Stamp */ |
||||
constexpr unsigned long TDTR_TIME_MASK = (0xFFFFU << TDTR_TIME_SHIFT); |
||||
|
||||
/* Mailbox data low register */ |
||||
|
||||
constexpr unsigned long TDLR_DATA0_SHIFT = (0U); /* Bits 7-0: Data Byte 0 */ |
||||
constexpr unsigned long TDLR_DATA0_MASK = (0xFFU << TDLR_DATA0_SHIFT); |
||||
constexpr unsigned long TDLR_DATA1_SHIFT = (8U); /* Bits 15-8: Data Byte 1 */ |
||||
constexpr unsigned long TDLR_DATA1_MASK = (0xFFU << TDLR_DATA1_SHIFT); |
||||
constexpr unsigned long TDLR_DATA2_SHIFT = (16U); /* Bits 23-16: Data Byte 2 */ |
||||
constexpr unsigned long TDLR_DATA2_MASK = (0xFFU << TDLR_DATA2_SHIFT); |
||||
constexpr unsigned long TDLR_DATA3_SHIFT = (24U); /* Bits 31-24: Data Byte 3 */ |
||||
constexpr unsigned long TDLR_DATA3_MASK = (0xFFU << TDLR_DATA3_SHIFT); |
||||
|
||||
/* Mailbox data high register */ |
||||
|
||||
constexpr unsigned long TDHR_DATA4_SHIFT = (0U); /* Bits 7-0: Data Byte 4 */ |
||||
constexpr unsigned long TDHR_DATA4_MASK = (0xFFU << TDHR_DATA4_SHIFT); |
||||
constexpr unsigned long TDHR_DATA5_SHIFT = (8U); /* Bits 15-8: Data Byte 5 */ |
||||
constexpr unsigned long TDHR_DATA5_MASK = (0xFFU << TDHR_DATA5_SHIFT); |
||||
constexpr unsigned long TDHR_DATA6_SHIFT = (16U); /* Bits 23-16: Data Byte 6 */ |
||||
constexpr unsigned long TDHR_DATA6_MASK = (0xFFU << TDHR_DATA6_SHIFT); |
||||
constexpr unsigned long TDHR_DATA7_SHIFT = (24U); /* Bits 31-24: Data Byte 7 */ |
||||
constexpr unsigned long TDHR_DATA7_MASK = (0xFFU << TDHR_DATA7_SHIFT); |
||||
|
||||
/* Rx FIFO mailbox identifier register */ |
||||
|
||||
constexpr unsigned long RIR_RTR = (1U << 1); /* Bit 1: Remote Transmission Request */ |
||||
constexpr unsigned long RIR_IDE = (1U << 2); /* Bit 2: Identifier Extension */ |
||||
constexpr unsigned long RIR_EXID_SHIFT = (3U); /* Bit 3-31: Extended Identifier */ |
||||
constexpr unsigned long RIR_EXID_MASK = (0x1FFFFFFFU << RIR_EXID_SHIFT); |
||||
constexpr unsigned long RIR_STID_SHIFT = (21U); /* Bits 21-31: Standard Identifier */ |
||||
constexpr unsigned long RIR_STID_MASK = (0x07FFU << RIR_STID_SHIFT); |
||||
|
||||
/* Receive FIFO mailbox data length control and time stamp register */ |
||||
|
||||
constexpr unsigned long RDTR_DLC_SHIFT = (0U); /* Bits 3:0: Data Length Code */ |
||||
constexpr unsigned long RDTR_DLC_MASK = (0x0FU << RDTR_DLC_SHIFT); |
||||
constexpr unsigned long RDTR_FM_SHIFT = (8U); /* Bits 15-8: Filter Match Index */ |
||||
constexpr unsigned long RDTR_FM_MASK = (0xFFU << RDTR_FM_SHIFT); |
||||
constexpr unsigned long RDTR_TIME_SHIFT = (16U); /* Bits 31:16: Message Time Stamp */ |
||||
constexpr unsigned long RDTR_TIME_MASK = (0xFFFFU << RDTR_TIME_SHIFT); |
||||
|
||||
/* Receive FIFO mailbox data low register */ |
||||
|
||||
constexpr unsigned long RDLR_DATA0_SHIFT = (0U); /* Bits 7-0: Data Byte 0 */ |
||||
constexpr unsigned long RDLR_DATA0_MASK = (0xFFU << RDLR_DATA0_SHIFT); |
||||
constexpr unsigned long RDLR_DATA1_SHIFT = (8U); /* Bits 15-8: Data Byte 1 */ |
||||
constexpr unsigned long RDLR_DATA1_MASK = (0xFFU << RDLR_DATA1_SHIFT); |
||||
constexpr unsigned long RDLR_DATA2_SHIFT = (16U); /* Bits 23-16: Data Byte 2 */ |
||||
constexpr unsigned long RDLR_DATA2_MASK = (0xFFU << RDLR_DATA2_SHIFT); |
||||
constexpr unsigned long RDLR_DATA3_SHIFT = (24U); /* Bits 31-24: Data Byte 3 */ |
||||
constexpr unsigned long RDLR_DATA3_MASK = (0xFFU << RDLR_DATA3_SHIFT); |
||||
|
||||
/* Receive FIFO mailbox data high register */ |
||||
|
||||
constexpr unsigned long RDHR_DATA4_SHIFT = (0U); /* Bits 7-0: Data Byte 4 */ |
||||
constexpr unsigned long RDHR_DATA4_MASK = (0xFFU << RDHR_DATA4_SHIFT); |
||||
constexpr unsigned long RDHR_DATA5_SHIFT = (8U); /* Bits 15-8: Data Byte 5 */ |
||||
constexpr unsigned long RDHR_DATA5_MASK = (0xFFU << RDHR_DATA5_SHIFT); |
||||
constexpr unsigned long RDHR_DATA6_SHIFT = (16U); /* Bits 23-16: Data Byte 6 */ |
||||
constexpr unsigned long RDHR_DATA6_MASK = (0xFFU << RDHR_DATA6_SHIFT); |
||||
constexpr unsigned long RDHR_DATA7_SHIFT = (24U); /* Bits 31-24: Data Byte 7 */ |
||||
constexpr unsigned long RDHR_DATA7_MASK = (0xFFU << RDHR_DATA7_SHIFT); |
||||
|
||||
/* CAN filter master register */ |
||||
|
||||
constexpr unsigned long FMR_FINIT = (1U << 0); /* Bit 0: Filter Init Mode */ |
||||
} |
||||
} |
||||
|
||||
#if UAVCAN_CPP_VERSION < UAVCAN_CPP11 |
||||
# undef constexpr |
||||
#endif |
||||
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Reference in new issue