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@ -110,32 +110,36 @@ void BusEvent::signalFromInterrupt()
@@ -110,32 +110,36 @@ void BusEvent::signalFromInterrupt()
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static void handleTxInterrupt(uint8_t iface_index) |
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{ |
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if (iface_index < CAN_STM32_NUM_IFACES) { |
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uint64_t utc_usec = clock::getUtcUSecFromCanInterrupt(); |
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if (iface_index >= CAN_STM32_NUM_IFACES) { |
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return; |
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} |
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uint64_t utc_usec = clock::getUtcUSecFromCanInterrupt(); |
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for (uint8_t i = 0; i < MAX_NUMBER_OF_CAN_DRIVERS; i++) { |
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if (hal.can_mgr[i] != nullptr) { |
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VRBRAINCAN* iface = ((VRBRAINCANManager*) hal.can_mgr[i])->getIface_out_to_in(iface_index); |
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if (iface != nullptr) { |
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iface->handleTxInterrupt(utc_usec); |
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} |
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} |
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for (uint8_t i = 0; i < MAX_NUMBER_OF_CAN_DRIVERS; i++) { |
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if (hal.can_mgr[i] == nullptr) { |
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continue; |
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} |
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VRBRAINCAN* iface = ((VRBRAINCANManager*) hal.can_mgr[i])->getIface_out_to_in(iface_index); |
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if (iface != nullptr) { |
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iface->handleTxInterrupt(utc_usec); |
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} |
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} |
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} |
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static void handleRxInterrupt(uint8_t iface_index, uint8_t fifo_index) |
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{ |
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if (iface_index < CAN_STM32_NUM_IFACES) { |
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uint64_t utc_usec = clock::getUtcUSecFromCanInterrupt(); |
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if (iface_index >= CAN_STM32_NUM_IFACES) { |
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return; |
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} |
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uint64_t utc_usec = clock::getUtcUSecFromCanInterrupt(); |
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for (uint8_t i = 0; i < MAX_NUMBER_OF_CAN_DRIVERS; i++) { |
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if (hal.can_mgr[i] != nullptr) { |
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VRBRAINCAN* iface = ((VRBRAINCANManager*) hal.can_mgr[i])->getIface_out_to_in(iface_index); |
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if (iface != nullptr) { |
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iface->handleRxInterrupt(fifo_index, utc_usec); |
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} |
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} |
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for (uint8_t i = 0; i < MAX_NUMBER_OF_CAN_DRIVERS; i++) { |
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if (hal.can_mgr[i] == nullptr) { |
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continue; |
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} |
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VRBRAINCAN* iface = ((VRBRAINCANManager*) hal.can_mgr[i])->getIface_out_to_in(iface_index); |
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if (iface != nullptr) { |
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iface->handleRxInterrupt(fifo_index, utc_usec); |
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} |
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} |
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} |
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@ -385,69 +389,69 @@ int16_t VRBRAINCAN::receive(uavcan::CanFrame& out_frame, uavcan::MonotonicTime&
@@ -385,69 +389,69 @@ int16_t VRBRAINCAN::receive(uavcan::CanFrame& out_frame, uavcan::MonotonicTime&
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int16_t VRBRAINCAN::configureFilters(const uavcan::CanFilterConfig* filter_configs, uint16_t num_configs) |
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{ |
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if (num_configs <= NumFilters) { |
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CriticalSectionLocker lock; |
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if (num_configs > NumFilters) { |
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return -ErrFilterNumConfigs; |
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} |
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can_->FMR |= bxcan::FMR_FINIT; |
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CriticalSectionLocker lock; |
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// Slave (CAN2) gets half of the filters
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can_->FMR = (can_->FMR & ~0x00003F00) | static_cast<uint32_t>(NumFilters) << 8; |
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can_->FMR |= bxcan::FMR_FINIT; |
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can_->FFA1R = 0x0AAAAAAA; // FIFO's are interleaved between filters
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can_->FM1R = 0; // Identifier Mask mode
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can_->FS1R = 0x7ffffff; // Single 32-bit for all
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// Slave (CAN2) gets half of the filters
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can_->FMR = (can_->FMR & ~0x00003F00) | static_cast<uint32_t>(NumFilters) << 8; |
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const uint8_t filter_start_index = (self_index_ == 0) ? 0 : NumFilters; |
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can_->FFA1R = 0x0AAAAAAA; // FIFO's are interleaved between filters
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can_->FM1R = 0; // Identifier Mask mode
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can_->FS1R = 0x7ffffff; // Single 32-bit for all
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if (num_configs == 0) { |
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can_->FilterRegister[filter_start_index].FR1 = 0; |
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can_->FilterRegister[filter_start_index].FR2 = 0; |
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can_->FA1R = 1 << filter_start_index; |
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} else { |
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for (uint8_t i = 0; i < NumFilters; i++) { |
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if (i < num_configs) { |
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uint32_t id = 0; |
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uint32_t mask = 0; |
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const uavcan::CanFilterConfig* const cfg = filter_configs + i; |
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if ((cfg->id & uavcan::CanFrame::FlagEFF) || !(cfg->mask & uavcan::CanFrame::FlagEFF)) { |
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id = (cfg->id & uavcan::CanFrame::MaskExtID) << 3; |
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mask = (cfg->mask & uavcan::CanFrame::MaskExtID) << 3; |
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id |= bxcan::RIR_IDE; |
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} else { |
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id = (cfg->id & uavcan::CanFrame::MaskStdID) << 21; |
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mask = (cfg->mask & uavcan::CanFrame::MaskStdID) << 21; |
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} |
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if (cfg->id & uavcan::CanFrame::FlagRTR) { |
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id |= bxcan::RIR_RTR; |
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} |
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if (cfg->mask & uavcan::CanFrame::FlagEFF) { |
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mask |= bxcan::RIR_IDE; |
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} |
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if (cfg->mask & uavcan::CanFrame::FlagRTR) { |
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mask |= bxcan::RIR_RTR; |
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} |
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can_->FilterRegister[filter_start_index + i].FR1 = id; |
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can_->FilterRegister[filter_start_index + i].FR2 = mask; |
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can_->FA1R |= (1 << (filter_start_index + i)); |
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const uint8_t filter_start_index = (self_index_ == 0) ? 0 : NumFilters; |
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if (num_configs == 0) { |
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can_->FilterRegister[filter_start_index].FR1 = 0; |
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can_->FilterRegister[filter_start_index].FR2 = 0; |
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can_->FA1R = 1 << filter_start_index; |
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} else { |
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for (uint8_t i = 0; i < NumFilters; i++) { |
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if (i < num_configs) { |
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uint32_t id = 0; |
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uint32_t mask = 0; |
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const uavcan::CanFilterConfig* const cfg = filter_configs + i; |
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if ((cfg->id & uavcan::CanFrame::FlagEFF) || !(cfg->mask & uavcan::CanFrame::FlagEFF)) { |
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id = (cfg->id & uavcan::CanFrame::MaskExtID) << 3; |
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mask = (cfg->mask & uavcan::CanFrame::MaskExtID) << 3; |
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id |= bxcan::RIR_IDE; |
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} else { |
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can_->FA1R &= ~(1 << (filter_start_index + i)); |
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id = (cfg->id & uavcan::CanFrame::MaskStdID) << 21; |
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mask = (cfg->mask & uavcan::CanFrame::MaskStdID) << 21; |
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} |
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} |
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} |
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can_->FMR &= ~bxcan::FMR_FINIT; |
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if (cfg->id & uavcan::CanFrame::FlagRTR) { |
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id |= bxcan::RIR_RTR; |
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} |
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return 0; |
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if (cfg->mask & uavcan::CanFrame::FlagEFF) { |
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mask |= bxcan::RIR_IDE; |
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} |
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if (cfg->mask & uavcan::CanFrame::FlagRTR) { |
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mask |= bxcan::RIR_RTR; |
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} |
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can_->FilterRegister[filter_start_index + i].FR1 = id; |
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can_->FilterRegister[filter_start_index + i].FR2 = mask; |
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can_->FA1R |= (1 << (filter_start_index + i)); |
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} else { |
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can_->FA1R &= ~(1 << (filter_start_index + i)); |
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} |
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} |
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} |
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return -ErrFilterNumConfigs; |
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can_->FMR &= ~bxcan::FMR_FINIT; |
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return 0; |
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} |
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bool VRBRAINCAN::waitMsrINakBitStateChange(bool target_state) |
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@ -564,22 +568,23 @@ int VRBRAINCAN::init(const uint32_t bitrate, const OperatingMode mode)
@@ -564,22 +568,23 @@ int VRBRAINCAN::init(const uint32_t bitrate, const OperatingMode mode)
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void VRBRAINCAN::handleTxMailboxInterrupt(uint8_t mailbox_index, bool txok, const uint64_t utc_usec) |
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{ |
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if (mailbox_index < NumTxMailboxes) { |
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had_activity_ = had_activity_ || txok; |
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if (mailbox_index >= NumTxMailboxes) { |
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return; |
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} |
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TxItem& txi = pending_tx_[mailbox_index]; |
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had_activity_ = had_activity_ || txok; |
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if (txi.loopback && txok && txi.pending) { |
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CanRxItem frm; |
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frm.frame = txi.frame; |
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frm.flags = uavcan::CanIOFlagLoopback; |
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frm.utc_usec = utc_usec; |
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rx_queue_.push(frm); |
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} |
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TxItem& txi = pending_tx_[mailbox_index]; |
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txi.pending = false; |
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if (txi.loopback && txok && txi.pending) { |
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CanRxItem frm; |
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frm.frame = txi.frame; |
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frm.flags = uavcan::CanIOFlagLoopback; |
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frm.utc_usec = utc_usec; |
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rx_queue_.push(frm); |
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} |
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txi.pending = false; |
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} |
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void VRBRAINCAN::handleTxInterrupt(const uint64_t utc_usec) |
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@ -610,83 +615,85 @@ void VRBRAINCAN::handleTxInterrupt(const uint64_t utc_usec)
@@ -610,83 +615,85 @@ void VRBRAINCAN::handleTxInterrupt(const uint64_t utc_usec)
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void VRBRAINCAN::handleRxInterrupt(uint8_t fifo_index, uint64_t utc_usec) |
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{ |
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if (fifo_index < 2) { |
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volatile uint32_t* const rfr_reg = (fifo_index == 0) ? &can_->RF0R : &can_->RF1R; |
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if ((*rfr_reg & bxcan::RFR_FMP_MASK) == 0) { |
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return; |
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} |
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if (fifo_index >= 2) { |
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return; |
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} |
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/*
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* Register overflow as a hardware error |
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*/ |
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if ((*rfr_reg & bxcan::RFR_FOVR) != 0) { |
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error_cnt_++; |
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} |
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volatile uint32_t* const rfr_reg = (fifo_index == 0) ? &can_->RF0R : &can_->RF1R; |
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if ((*rfr_reg & bxcan::RFR_FMP_MASK) == 0) { |
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return; |
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} |
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/*
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* Read the frame contents |
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*/ |
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uavcan::CanFrame frame; |
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const bxcan::RxMailboxType& rf = can_->RxMailbox[fifo_index]; |
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/*
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* Register overflow as a hardware error |
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*/ |
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if ((*rfr_reg & bxcan::RFR_FOVR) != 0) { |
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error_cnt_++; |
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} |
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if ((rf.RIR & bxcan::RIR_IDE) == 0) { |
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frame.id = uavcan::CanFrame::MaskStdID & (rf.RIR >> 21); |
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} else { |
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frame.id = uavcan::CanFrame::MaskExtID & (rf.RIR >> 3); |
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frame.id |= uavcan::CanFrame::FlagEFF; |
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} |
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/*
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* Read the frame contents |
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*/ |
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uavcan::CanFrame frame; |
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const bxcan::RxMailboxType& rf = can_->RxMailbox[fifo_index]; |
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if ((rf.RIR & bxcan::RIR_RTR) != 0) { |
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frame.id |= uavcan::CanFrame::FlagRTR; |
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} |
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if ((rf.RIR & bxcan::RIR_IDE) == 0) { |
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frame.id = uavcan::CanFrame::MaskStdID & (rf.RIR >> 21); |
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} else { |
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frame.id = uavcan::CanFrame::MaskExtID & (rf.RIR >> 3); |
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frame.id |= uavcan::CanFrame::FlagEFF; |
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} |
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frame.dlc = rf.RDTR & 15; |
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if ((rf.RIR & bxcan::RIR_RTR) != 0) { |
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frame.id |= uavcan::CanFrame::FlagRTR; |
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} |
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frame.data[0] = uint8_t(0xFF & (rf.RDLR >> 0)); |
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frame.data[1] = uint8_t(0xFF & (rf.RDLR >> 8)); |
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frame.data[2] = uint8_t(0xFF & (rf.RDLR >> 16)); |
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frame.data[3] = uint8_t(0xFF & (rf.RDLR >> 24)); |
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frame.data[4] = uint8_t(0xFF & (rf.RDHR >> 0)); |
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frame.data[5] = uint8_t(0xFF & (rf.RDHR >> 8)); |
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frame.data[6] = uint8_t(0xFF & (rf.RDHR >> 16)); |
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frame.data[7] = uint8_t(0xFF & (rf.RDHR >> 24)); |
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frame.dlc = rf.RDTR & 15; |
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*rfr_reg = bxcan::RFR_RFOM | bxcan::RFR_FOVR | bxcan::RFR_FULL; // Release FIFO entry we just read
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frame.data[0] = uint8_t(0xFF & (rf.RDLR >> 0)); |
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frame.data[1] = uint8_t(0xFF & (rf.RDLR >> 8)); |
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frame.data[2] = uint8_t(0xFF & (rf.RDLR >> 16)); |
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frame.data[3] = uint8_t(0xFF & (rf.RDLR >> 24)); |
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frame.data[4] = uint8_t(0xFF & (rf.RDHR >> 0)); |
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frame.data[5] = uint8_t(0xFF & (rf.RDHR >> 8)); |
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frame.data[6] = uint8_t(0xFF & (rf.RDHR >> 16)); |
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frame.data[7] = uint8_t(0xFF & (rf.RDHR >> 24)); |
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/*
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* Store with timeout into the FIFO buffer and signal update event |
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*/ |
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CanRxItem frm; |
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frm.frame = frame; |
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frm.flags = 0; |
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frm.utc_usec = utc_usec; |
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rx_queue_.push(frm); |
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|
*rfr_reg = bxcan::RFR_RFOM | bxcan::RFR_FOVR | bxcan::RFR_FULL; // Release FIFO entry we just read
|
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|
had_activity_ = true; |
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|
|
|
if(update_event_ != nullptr) { |
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|
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|
update_event_->signalFromInterrupt(); |
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|
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|
} |
|
|
|
|
/*
|
|
|
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|
* Store with timeout into the FIFO buffer and signal update event |
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|
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|
*/ |
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|
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|
CanRxItem frm; |
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|
frm.frame = frame; |
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|
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|
frm.flags = 0; |
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|
frm.utc_usec = utc_usec; |
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|
rx_queue_.push(frm); |
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|
pollErrorFlagsFromISR(); |
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|
had_activity_ = true; |
|
|
|
|
if(update_event_ != nullptr) { |
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|
update_event_->signalFromInterrupt(); |
|
|
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|
} |
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|
pollErrorFlagsFromISR(); |
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|
} |
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|
void VRBRAINCAN::pollErrorFlagsFromISR() |
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|
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|
{ |
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|
|
const uint8_t lec = uint8_t((can_->ESR & bxcan::ESR_LEC_MASK) >> bxcan::ESR_LEC_SHIFT); |
|
|
|
|
if (lec != 0) { |
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|
|
can_->ESR = 0; |
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|
error_cnt_++; |
|
|
|
|
if (lec == 0) { |
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|
return; |
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|
} |
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|
can_->ESR = 0; |
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|
error_cnt_++; |
|
|
|
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|
|
// Serving abort requests
|
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|
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|
for (int i = 0; i < NumTxMailboxes; i++) { // Dear compiler, may I suggest you to unroll this loop please.
|
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|
|
|
TxItem& txi = pending_tx_[i]; |
|
|
|
|
if (txi.pending && txi.abort_on_error) { |
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|
|
|
can_->TSR = TSR_ABRQx[i]; |
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|
|
txi.pending = false; |
|
|
|
|
served_aborts_cnt_++; |
|
|
|
|
} |
|
|
|
|
// Serving abort requests
|
|
|
|
|
for (int i = 0; i < NumTxMailboxes; i++) { // Dear compiler, may I suggest you to unroll this loop please.
|
|
|
|
|
TxItem& txi = pending_tx_[i]; |
|
|
|
|
if (txi.pending && txi.abort_on_error) { |
|
|
|
|
can_->TSR = TSR_ABRQx[i]; |
|
|
|
|
txi.pending = false; |
|
|
|
|
served_aborts_cnt_++; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
@ -799,10 +806,12 @@ int32_t VRBRAINCAN::available()
@@ -799,10 +806,12 @@ int32_t VRBRAINCAN::available()
|
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|
|
|
|
|
|
|
int32_t VRBRAINCAN::tx_pending() |
|
|
|
|
{ |
|
|
|
|
int32_t ret = -1; |
|
|
|
|
if (!initialized_) { |
|
|
|
|
return -1; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (initialized_) { |
|
|
|
|
ret = 0; |
|
|
|
|
int32_t ret = 0; |
|
|
|
|
{ |
|
|
|
|
CriticalSectionLocker lock; |
|
|
|
|
|
|
|
|
|
for (int mbx = 0; mbx < NumTxMailboxes; mbx++) { |
|
|
|
@ -811,7 +820,6 @@ int32_t VRBRAINCAN::tx_pending()
@@ -811,7 +820,6 @@ int32_t VRBRAINCAN::tx_pending()
|
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
return ret; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
@ -835,16 +843,19 @@ uavcan::CanSelectMasks VRBRAINCANManager::makeSelectMasks(const uavcan::CanFrame
@@ -835,16 +843,19 @@ uavcan::CanSelectMasks VRBRAINCANManager::makeSelectMasks(const uavcan::CanFrame
|
|
|
|
|
uavcan::CanSelectMasks msk; |
|
|
|
|
|
|
|
|
|
for (uint8_t i = 0; i < _ifaces_num; i++) { |
|
|
|
|
if (ifaces[i] != nullptr) { |
|
|
|
|
if (!ifaces[i]->isRxBufferEmpty()) { |
|
|
|
|
msk.read |= 1 << i; |
|
|
|
|
} |
|
|
|
|
if (ifaces[i] == nullptr) { |
|
|
|
|
continue; |
|
|
|
|
} |
|
|
|
|
if (!ifaces[i]->isRxBufferEmpty()) { |
|
|
|
|
msk.read |= 1 << i; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (pending_tx[i] != nullptr) { |
|
|
|
|
if (ifaces[i]->canAcceptNewTxFrame(*pending_tx[i])) { |
|
|
|
|
msk.write |= 1 << i; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
if (pending_tx[i] == nullptr) { |
|
|
|
|
continue; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (ifaces[i]->canAcceptNewTxFrame(*pending_tx[i])) { |
|
|
|
|
msk.write |= 1 << i; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
@ -871,12 +882,13 @@ int16_t VRBRAINCANManager::select(uavcan::CanSelectMasks& inout_masks,
@@ -871,12 +882,13 @@ int16_t VRBRAINCANManager::select(uavcan::CanSelectMasks& inout_masks,
|
|
|
|
|
const uavcan::MonotonicTime time = clock::getMonotonic(); |
|
|
|
|
|
|
|
|
|
for (uint8_t i = 0; i < _ifaces_num; i++) { |
|
|
|
|
if (ifaces[i] != nullptr) { |
|
|
|
|
ifaces[i]->discardTimedOutTxMailboxes(time); |
|
|
|
|
{ |
|
|
|
|
CriticalSectionLocker cs_locker; |
|
|
|
|
ifaces[i]->pollErrorFlagsFromISR(); |
|
|
|
|
} |
|
|
|
|
if (ifaces[i] == nullptr) { |
|
|
|
|
continue; |
|
|
|
|
} |
|
|
|
|
ifaces[i]->discardTimedOutTxMailboxes(time); |
|
|
|
|
{ |
|
|
|
|
CriticalSectionLocker cs_locker; |
|
|
|
|
ifaces[i]->pollErrorFlagsFromISR(); |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
@ -951,62 +963,63 @@ void VRBRAINCANManager::initOnce(uint8_t can_number)
@@ -951,62 +963,63 @@ void VRBRAINCANManager::initOnce(uint8_t can_number)
|
|
|
|
|
|
|
|
|
|
int VRBRAINCANManager::init(const uint32_t bitrate, const VRBRAINCAN::OperatingMode mode, uint8_t can_number) |
|
|
|
|
{ |
|
|
|
|
int res = -ErrNotImplemented; |
|
|
|
|
static bool initialized_once[CAN_STM32_NUM_IFACES]; |
|
|
|
|
|
|
|
|
|
if (can_number < CAN_STM32_NUM_IFACES) { |
|
|
|
|
res = 0; |
|
|
|
|
if (can_number >= CAN_STM32_NUM_IFACES) { |
|
|
|
|
return -ErrNotImplemented; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(can_number) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init Bitrate %lu mode %d bus %d\n\r", static_cast<unsigned long>(bitrate), |
|
|
|
|
static_cast<int>(mode), static_cast<int>(can_number)); |
|
|
|
|
} |
|
|
|
|
int res = 0; |
|
|
|
|
|
|
|
|
|
// If this outside physical interface was never inited - do this and add it to in/out conversion tables
|
|
|
|
|
if (!initialized_once[can_number]) { |
|
|
|
|
initialized_once[can_number] = true; |
|
|
|
|
_ifaces_num++; |
|
|
|
|
_ifaces_out_to_in[can_number] = _ifaces_num - 1; |
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(can_number) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init Bitrate %lu mode %d bus %d\n\r", static_cast<unsigned long>(bitrate), |
|
|
|
|
static_cast<int>(mode), static_cast<int>(can_number)); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(can_number) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init First initialization bus %d\n\r", static_cast<int>(can_number)); |
|
|
|
|
} |
|
|
|
|
// If this outside physical interface was never inited - do this and add it to in/out conversion tables
|
|
|
|
|
if (!initialized_once[can_number]) { |
|
|
|
|
initialized_once[can_number] = true; |
|
|
|
|
_ifaces_num++; |
|
|
|
|
_ifaces_out_to_in[can_number] = _ifaces_num - 1; |
|
|
|
|
|
|
|
|
|
initOnce(can_number); |
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(can_number) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init First initialization bus %d\n\r", static_cast<int>(can_number)); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* CAN1 |
|
|
|
|
*/ |
|
|
|
|
if (can_number == 0) { |
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(0) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init Initing iface 0...\n\r"); |
|
|
|
|
} |
|
|
|
|
ifaces[_ifaces_out_to_in[can_number]] = &if0_; // This link must be initialized first,
|
|
|
|
|
initOnce(can_number); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* CAN1 |
|
|
|
|
*/ |
|
|
|
|
if (can_number == 0) { |
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(0) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init Initing iface 0...\n\r"); |
|
|
|
|
} |
|
|
|
|
ifaces[_ifaces_out_to_in[can_number]] = &if0_; // This link must be initialized first,
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
#if CAN_STM32_NUM_IFACES > 1 |
|
|
|
|
/*
|
|
|
|
|
* CAN2 |
|
|
|
|
*/ |
|
|
|
|
if (can_number == 1) { |
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(1) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init Initing iface 1...\n\r"); |
|
|
|
|
} |
|
|
|
|
ifaces[_ifaces_out_to_in[can_number]] = &if1_; // Same thing here.
|
|
|
|
|
/*
|
|
|
|
|
* CAN2 |
|
|
|
|
*/ |
|
|
|
|
if (can_number == 1) { |
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(1) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init Initing iface 1...\n\r"); |
|
|
|
|
} |
|
|
|
|
ifaces[_ifaces_out_to_in[can_number]] = &if1_; // Same thing here.
|
|
|
|
|
} |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
ifaces[_ifaces_out_to_in[can_number]]->set_update_event(&update_event_); |
|
|
|
|
res = ifaces[_ifaces_out_to_in[can_number]]->init(bitrate, mode); |
|
|
|
|
if (res < 0) { |
|
|
|
|
ifaces[_ifaces_out_to_in[can_number]] = nullptr; |
|
|
|
|
return res; |
|
|
|
|
} |
|
|
|
|
ifaces[_ifaces_out_to_in[can_number]]->set_update_event(&update_event_); |
|
|
|
|
res = ifaces[_ifaces_out_to_in[can_number]]->init(bitrate, mode); |
|
|
|
|
if (res < 0) { |
|
|
|
|
ifaces[_ifaces_out_to_in[can_number]] = nullptr; |
|
|
|
|
return res; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(can_number) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init CAN drv init OK, res = %d\n\r", res); |
|
|
|
|
} |
|
|
|
|
if (AP_BoardConfig_CAN::get_can_debug(can_number) >= 2) { |
|
|
|
|
printf("VRBRAINCANManager::init CAN drv init OK, res = %d\n\r", res); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
return res; |
|
|
|
|