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@ -19,7 +19,7 @@
@@ -19,7 +19,7 @@
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#pragma once |
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// we want to cope with both revision XY chips and newer chips
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#ifndef STM32H750xx |
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#if !defined(HAL_CUSTOM_MCU_CLOCKRATE) || HAL_CUSTOM_MCU_CLOCKRATE <= 400000000 |
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#define STM32_ENFORCE_H7_REV_XY |
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#endif |
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@ -161,9 +161,13 @@
@@ -161,9 +161,13 @@
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#elif (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U) |
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// common clock tree for multiples of 8MHz crystals
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#ifdef STM32H750xx |
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#ifdef HAL_CUSTOM_MCU_CLOCKRATE |
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#if HAL_CUSTOM_MCU_CLOCKRATE == 480000000 |
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#define STM32_PLL1_DIVN_VALUE 120 |
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#else |
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#error "Unable to configure custom clockrate" |
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#endif |
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#else |
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#define STM32_PLL1_DIVN_VALUE 100 |
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#endif |
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#define STM32_PLL1_DIVP_VALUE 2 |
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@ -181,9 +185,13 @@
@@ -181,9 +185,13 @@
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#define STM32_PLL3_DIVR_VALUE 9 |
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#elif STM32_HSECLK == 24000000U |
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#ifdef STM32H750xx |
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#ifdef HAL_CUSTOM_MCU_CLOCKRATE |
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#if HAL_CUSTOM_MCU_CLOCKRATE == 480000000 |
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#define STM32_PLL1_DIVN_VALUE 120 |
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#else |
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#error "Unable to configure custom clockrate" |
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#endif |
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#else |
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#define STM32_PLL1_DIVN_VALUE 100 |
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#endif |
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#define STM32_PLL1_DIVP_VALUE 2 |
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@ -201,6 +209,9 @@
@@ -201,6 +209,9 @@
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#define STM32_PLL3_DIVR_VALUE 9 |
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#elif STM32_HSECLK == 25000000U |
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#ifdef HAL_CUSTOM_MCU_CLOCKRATE |
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#error "Unable to configure custom clockrate" |
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#endif |
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#define STM32_PLL1_DIVN_VALUE 64 |
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#define STM32_PLL1_DIVP_VALUE 2 |
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#define STM32_PLL1_DIVQ_VALUE 10 |
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