3 Commits (8046fe2cf30e84735e6566bb6c9e29dceac0ebae)

Author SHA1 Message Date
Andrew Tridgell 7ecf8981b9 SITL: added dummy SPI and make RCInput 50Hz 12 years ago
Andrew Tridgell e020694c03 SITL: fixed build of apm1/apm2 target 12 years ago
Andrew Tridgell 0c9d37e2ee SITL: added RCInput and RCOutput 12 years ago