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130 lines
6.0 KiB
130 lines
6.0 KiB
/* |
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MPU defines |
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see ST AN4838 |
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(c) 2017 night_ghost@ykoctpa.ru |
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based on: datasheet |
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*/ |
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#pragma once |
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#define MPU_TYPE_SEPARATED (1U << 0U) |
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#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U) |
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#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U) |
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#define MPU_CTRL_ENABLE MPU_CTRL_ENABLE_Msk |
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#define MPU_CTRL_HFNMIENA MPU_CTRL_HFNMIENA_Msk |
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#define MPU_CTRL_PRIVDEFENA MPU_CTRL_PRIVDEFENA_Msk |
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#define MPU_RNR_REGION MPU_RNR_REGION_Msk |
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#define MPU_RBAR_REGION_MASK MPU_RBAR_REGION_Msk |
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#define MPU_RBAR_VALID MPU_RBAR_VALID_Msk |
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#define MPU_RBAR_ADDR_MASK MPU_RBAR_ADDR_Msk |
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#define MPU_RASR_ENABLE MPU_RASR_ENABLE_Msk |
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#define MPU_RASR_SIZE_MASK MPU_RASR_SIZE_Msk |
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#define MPU_RASR_SIZE(n) ((n) << MPU_RASR_SIZE_Pos) |
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#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4) |
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#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5) |
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#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6) |
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#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7) |
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#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8) |
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#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9) |
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#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10) |
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#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11) |
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#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12) |
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#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13) |
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#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14) |
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#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15) |
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#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16) |
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#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17) |
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#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18) |
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#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19) |
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#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20) |
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#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21) |
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#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22) |
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#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23) |
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#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24) |
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#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25) |
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#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26) |
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#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27) |
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#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28) |
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#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29) |
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#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30) |
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#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31) |
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#define MPU_RASR_SRD_MASK MPU_RASR_SRD_Msk |
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#define MPU_RASR_SRD(n) ((n) << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_ALL (0U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_DISABLE_SUB0 (1U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_DISABLE_SUB1 (2U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_DISABLE_SUB2 (4U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_DISABLE_SUB3 (8U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_DISABLE_SUB4 (16U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_DISABLE_SUB5 (32U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_DISABLE_SUB6 (64U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_SRD_DISABLE_SUB7 (128U << MPU_RASR_SRD_Pos) |
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#define MPU_RASR_ATTR_B MPU_RASR_B_Msk |
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#define MPU_RASR_ATTR_C MPU_RASR_C_Msk |
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#define MPU_RASR_ATTR_S MPU_RASR_S_Msk |
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#define MPU_RASR_ATTR_TEX_MASK MPU_RASR_TEX_Msk |
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#define MPU_RASR_ATTR_TEX(n) ((n) << MPU_RASR_TEX_Pos) |
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#define MPU_RASR_ATTR_AP_MASK MPU_RASR_AP_Msk |
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#define MPU_RASR_ATTR_AP(n) ((n) << MPU_RASR_AP_Pos) |
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#define MPU_RASR_ATTR_XN MPU_RASR_XN_Msk |
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// Human Readable region attributes |
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#define MPU_RASR_ATTR_AP_NA_NA (0U << MPU_RASR_AP_Pos) |
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#define MPU_RASR_ATTR_AP_RW_NA (1U << MPU_RASR_AP_Pos) |
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#define MPU_RASR_ATTR_AP_RW_RO (2U << MPU_RASR_AP_Pos) |
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#define MPU_RASR_ATTR_AP_RW_RW (3U << MPU_RASR_AP_Pos) |
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#define MPU_RASR_ATTR_AP_RO_NA (5U << MPU_RASR_AP_Pos) |
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#define MPU_RASR_ATTR_AP_RO_RO (6U << MPU_RASR_AP_Pos) |
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#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0)) |
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#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B) |
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#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C) |
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#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) |
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#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1)) |
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#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) |
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#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2)) |
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#define MPU_REGION_0 0 |
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#define MPU_REGION_1 1 |
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#define MPU_REGION_2 2 |
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#define MPU_REGION_3 3 |
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#define MPU_REGION_4 4 |
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#define MPU_REGION_5 5 |
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#define MPU_REGION_6 6 |
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#define MPU_REGION_7 7 |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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static inline void mpu_enable(uint32_t ctrl) { |
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MPU->CTRL = ctrl | MPU_CTRL_ENABLE; // flags + Enable |
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; // enable MemManage fault |
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} |
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static inline void mpu_disable() { |
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// SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; // disable MemManage fault |
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MPU->CTRL = 0; // disable |
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asm volatile("DSB"); // see PM0214 (en.DM00046982.pdf) page 196 |
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} |
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static inline void mpu_configure_region(uint8_t region, uint32_t addr, uint32_t attribs) { |
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MPU->RASR = 0; // disable region first |
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MPU->RBAR = (addr & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID; // set region number and address |
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MPU->RASR = attribs | MPU_RASR_ENABLE; // set flags and enable region |
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} |
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#ifdef __cplusplus |
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} |
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#endif
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