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548 lines
14 KiB
548 lines
14 KiB
/************************************************************************************ |
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* Copyright (C) 2011 Uros Platise. All rights reserved. |
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* Author: Uros Platise <uros.platise@isotel.eu> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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/* |
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* This file is free software: you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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* See the GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program. If not, see <http://www.gnu.org/licenses/>. |
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* |
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* Modified for use in AP_HAL by Andrew Tridgell and Siddharth Bharat Purohit |
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*/ |
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#include "flash.h" |
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#include "hal.h" |
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#include <string.h> |
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// #pragma GCC optimize("O0") |
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/* |
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this driver has been tested with STM32F427 and STM32F412 |
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*/ |
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#ifndef HAL_NO_FLASH_SUPPORT |
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#ifndef BOARD_FLASH_SIZE |
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#error "You must define BOARD_FLASH_SIZE in kbyte" |
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#endif |
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#define KB(x) ((x*1024)) |
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// Refer Flash memory map in the User Manual to fill the following fields per microcontroller |
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#define STM32_FLASH_BASE 0x08000000 |
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#define STM32_FLASH_SIZE KB(BOARD_FLASH_SIZE) |
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// optionally disable interrupts during flash writes |
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#define STM32_FLASH_DISABLE_ISR 0 |
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// the 2nd bank of flash needs to be handled differently |
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#define STM32_FLASH_BANK2_START (STM32_FLASH_BASE+0x00080000) |
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#if defined(STM32F4) |
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#if BOARD_FLASH_SIZE == 512 |
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#define STM32_FLASH_NPAGES 7 |
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static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(16), KB(16), KB(16), KB(16), KB(64), |
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KB(128), KB(128), KB(128) }; |
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#elif BOARD_FLASH_SIZE == 1024 |
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#define STM32_FLASH_NPAGES 12 |
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static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(16), KB(16), KB(16), KB(16), KB(64), |
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KB(128), KB(128), KB(128), KB(128), KB(128), KB(128), KB(128) }; |
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#elif BOARD_FLASH_SIZE == 2048 |
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#define STM32_FLASH_NPAGES 24 |
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static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(16), KB(16), KB(16), KB(16), KB(64), |
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KB(128), KB(128), KB(128), KB(128), KB(128), KB(128), KB(128), |
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KB(16), KB(16), KB(16), KB(16), KB(64), |
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KB(128), KB(128), KB(128), KB(128), KB(128), KB(128), KB(128)}; |
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#else |
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#error "BOARD_FLASH_SIZE invalid" |
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#endif |
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#elif defined(STM32F7) |
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#if BOARD_FLASH_SIZE == 1024 |
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#define STM32_FLASH_NPAGES 8 |
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static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(32), KB(32), KB(32), KB(32), KB(128), KB(256), KB(256), KB(256) }; |
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#elif BOARD_FLASH_SIZE == 2048 |
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#define STM32_FLASH_NPAGES 12 |
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static const uint32_t flash_memmap[STM32_FLASH_NPAGES] = { KB(32), KB(32), KB(32), KB(32), KB(128), KB(256), KB(256), KB(256), |
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KB(256), KB(256), KB(256), KB(256) }; |
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#else |
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#error "BOARD_FLASH_SIZE invalid" |
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#endif |
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#elif defined(STM32H7) |
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#define STM32_FLASH_NPAGES (BOARD_FLASH_SIZE / 128) |
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#define STM32_FLASH_FIXED_PAGE_SIZE 128 |
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#else |
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#error "Unsupported processor for flash.c" |
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#endif |
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// keep a cache of the page addresses |
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#ifndef STM32_FLASH_FIXED_PAGE_SIZE |
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static uint32_t flash_pageaddr[STM32_FLASH_NPAGES]; |
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static bool flash_pageaddr_initialised; |
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#endif |
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static bool flash_keep_unlocked; |
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#define FLASH_KEY1 0x45670123 |
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#define FLASH_KEY2 0xCDEF89AB |
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/* Some compiler options will convert short loads and stores into byte loads |
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* and stores. We don't want this to happen for IO reads and writes! |
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*/ |
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/* # define getreg16(a) (*(volatile uint16_t *)(a)) */ |
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static inline uint16_t getreg16(unsigned int addr) |
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{ |
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uint16_t retval; |
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__asm__ __volatile__("\tldrh %0, [%1]\n\t" : "=r"(retval) : "r"(addr)); |
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return retval; |
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} |
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/* define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) */ |
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static inline void putreg16(uint16_t val, unsigned int addr) |
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{ |
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__asm__ __volatile__("\tstrh %0, [%1]\n\t": : "r"(val), "r"(addr)); |
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} |
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/* # define getreg32(a) (*(volatile uint32_t *)(a)) */ |
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static inline uint32_t getreg32(unsigned int addr) |
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{ |
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uint32_t retval; |
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__asm__ __volatile__("\tldr %0, [%1]\n\t" : "=r"(retval) : "r"(addr)); |
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return retval; |
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} |
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/* define putreg32(v,a) */ |
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static inline void putreg32(uint32_t val, unsigned int addr) |
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{ |
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*(volatile uint32_t *)(addr) = val; |
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} |
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static void stm32_flash_wait_idle(void) |
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{ |
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__DSB(); |
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#if defined(STM32H7) |
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while ((FLASH->SR1 & (FLASH_SR_BSY|FLASH_SR_QW|FLASH_SR_WBNE)) || |
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(FLASH->SR2 & (FLASH_SR_BSY|FLASH_SR_QW|FLASH_SR_WBNE))) { |
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// nop |
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} |
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#else |
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while (FLASH->SR & FLASH_SR_BSY) { |
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// nop |
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} |
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#endif |
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} |
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static void stm32_flash_clear_errors(void) |
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{ |
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#if defined(STM32H7) |
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FLASH->CCR1 = ~0; |
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FLASH->CCR2 = ~0; |
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#else |
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FLASH->SR = 0xF3; |
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#endif |
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} |
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static void stm32_flash_unlock(void) |
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{ |
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if (flash_keep_unlocked) { |
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return; |
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} |
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stm32_flash_wait_idle(); |
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#if defined(STM32H7) |
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if (FLASH->CR1 & FLASH_CR_LOCK) { |
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/* Unlock sequence */ |
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FLASH->KEYR1 = FLASH_KEY1; |
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FLASH->KEYR1 = FLASH_KEY2; |
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} |
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if (FLASH->CR2 & FLASH_CR_LOCK) { |
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/* Unlock sequence */ |
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FLASH->KEYR2 = FLASH_KEY1; |
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FLASH->KEYR2 = FLASH_KEY2; |
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} |
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#else |
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if (FLASH->CR & FLASH_CR_LOCK) { |
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/* Unlock sequence */ |
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FLASH->KEYR = FLASH_KEY1; |
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FLASH->KEYR = FLASH_KEY2; |
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} |
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#endif |
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#ifdef FLASH_ACR_DCEN |
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// disable the data cache - see stm32 errata 2.1.11 |
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FLASH->ACR &= ~FLASH_ACR_DCEN; |
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#endif |
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} |
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void stm32_flash_lock(void) |
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{ |
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if (flash_keep_unlocked) { |
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return; |
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} |
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#if defined(STM32H7) |
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if (FLASH->SR1 & FLASH_SR_QW) { |
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FLASH->CR1 |= FLASH_CR_FW; |
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} |
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if (FLASH->SR2 & FLASH_SR_QW) { |
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FLASH->CR2 |= FLASH_CR_FW; |
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} |
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stm32_flash_wait_idle(); |
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FLASH->CR1 |= FLASH_CR_LOCK; |
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FLASH->CR2 |= FLASH_CR_LOCK; |
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#else |
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stm32_flash_wait_idle(); |
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FLASH->CR |= FLASH_CR_LOCK; |
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#endif |
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#ifdef FLASH_ACR_DCEN |
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// reset and re-enable the data cache - see stm32 errata 2.1.11 |
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FLASH->ACR |= FLASH_ACR_DCRST; |
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FLASH->ACR &= ~FLASH_ACR_DCRST; |
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FLASH->ACR |= FLASH_ACR_DCEN; |
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#endif |
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} |
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/* |
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get the memory address of a page |
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*/ |
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uint32_t stm32_flash_getpageaddr(uint32_t page) |
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{ |
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if (page >= STM32_FLASH_NPAGES) { |
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return 0; |
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} |
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#if defined(STM32_FLASH_FIXED_PAGE_SIZE) |
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return STM32_FLASH_BASE + page * STM32_FLASH_FIXED_PAGE_SIZE * 1024; |
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#else |
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if (!flash_pageaddr_initialised) { |
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uint32_t address = STM32_FLASH_BASE; |
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uint8_t i; |
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for (i = 0; i < STM32_FLASH_NPAGES; i++) { |
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flash_pageaddr[i] = address; |
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address += stm32_flash_getpagesize(i); |
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} |
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flash_pageaddr_initialised = true; |
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} |
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return flash_pageaddr[page]; |
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#endif |
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} |
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/* |
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get size in bytes of a page |
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*/ |
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uint32_t stm32_flash_getpagesize(uint32_t page) |
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{ |
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#if defined(STM32_FLASH_FIXED_PAGE_SIZE) |
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(void)page; |
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return STM32_FLASH_FIXED_PAGE_SIZE * 1024; |
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#else |
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return flash_memmap[page]; |
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#endif |
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} |
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/* |
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return total number of pages |
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*/ |
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uint32_t stm32_flash_getnumpages() |
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{ |
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return STM32_FLASH_NPAGES; |
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} |
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bool stm32_flash_ispageerased(uint32_t page) |
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{ |
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uint32_t addr; |
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uint32_t count; |
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if (page >= STM32_FLASH_NPAGES) { |
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return false; |
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} |
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for (addr = stm32_flash_getpageaddr(page), count = stm32_flash_getpagesize(page); |
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count; count -= 4, addr += 4) { |
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uint32_t v = getreg32(addr); |
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if (v != 0xffffffff) { |
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return false; |
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} |
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} |
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return true; |
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} |
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/* |
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erase a page |
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*/ |
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bool stm32_flash_erasepage(uint32_t page) |
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{ |
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if (page >= STM32_FLASH_NPAGES) { |
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return false; |
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} |
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#if STM32_FLASH_DISABLE_ISR |
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syssts_t sts = chSysGetStatusAndLockX(); |
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#endif |
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stm32_flash_wait_idle(); |
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stm32_flash_unlock(); |
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// clear any previous errors |
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stm32_flash_clear_errors(); |
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#if defined(STM32H7) |
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if (page < 8) { |
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// first bank |
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FLASH->SR1 = ~0; |
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stm32_flash_wait_idle(); |
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uint32_t snb = page << 8; |
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// use 32 bit operations |
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FLASH->CR1 = FLASH_CR_PSIZE_1 | snb | FLASH_CR_SER; |
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FLASH->CR1 |= FLASH_CR_START; |
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while (FLASH->SR1 & FLASH_SR_QW) ; |
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} else { |
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// second bank |
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FLASH->SR2 = ~0; |
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stm32_flash_wait_idle(); |
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uint32_t snb = (page-8) << 8; |
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// use 32 bit operations |
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FLASH->CR2 = FLASH_CR_PSIZE_1 | snb | FLASH_CR_SER; |
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FLASH->CR2 |= FLASH_CR_START; |
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while (FLASH->SR2 & FLASH_SR_QW) ; |
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} |
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#else |
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stm32_flash_wait_idle(); |
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// the snb mask is not contiguous, calculate the mask for the page |
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uint8_t snb = (((page % 12) << 3) | ((page / 12) << 7)); |
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// use 32 bit operations |
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FLASH->CR = FLASH_CR_PSIZE_1 | snb | FLASH_CR_SER; |
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FLASH->CR |= FLASH_CR_STRT; |
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#endif |
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stm32_flash_wait_idle(); |
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cacheBufferInvalidate(stm32_flash_getpageaddr(page), stm32_flash_getpagesize(page)); |
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stm32_flash_lock(); |
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#if STM32_FLASH_DISABLE_ISR |
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chSysRestoreStatusX(sts); |
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#endif |
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return stm32_flash_ispageerased(page); |
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} |
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#if defined(STM32H7) |
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/* |
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the H7 needs special handling, and only writes 32 bytes at a time |
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*/ |
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static bool stm32h7_flash_write32(uint32_t addr, const void *buf) |
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{ |
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volatile uint32_t *CR, *CCR, *SR; |
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if (addr - STM32_FLASH_BASE < 8 * STM32_FLASH_FIXED_PAGE_SIZE * 1024) { |
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CR = &FLASH->CR1; |
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CCR = &FLASH->CCR1; |
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SR = &FLASH->SR1; |
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} else { |
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CR = &FLASH->CR2; |
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CCR = &FLASH->CCR2; |
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SR = &FLASH->SR2; |
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} |
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stm32_flash_wait_idle(); |
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*CCR = ~0; |
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*CR |= FLASH_CR_PG; |
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const uint32_t *v = (const uint32_t *)buf; |
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uint8_t i; |
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for (i=0; i<8; i++) { |
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while (*SR & (FLASH_SR_BSY|FLASH_SR_QW)) ; |
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putreg32(*v, addr); |
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v++; |
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addr += 4; |
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} |
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__DSB(); |
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stm32_flash_wait_idle(); |
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*CCR = ~0; |
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*CR &= ~FLASH_CR_PG; |
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return true; |
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} |
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bool stm32_flash_write(uint32_t addr, const void *buf, uint32_t count) |
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{ |
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uint8_t *b = (uint8_t *)buf; |
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if ((count & 0x1F) || (addr & 0x1F)) { |
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// only allow 256 bit aligned writes |
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return false; |
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} |
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stm32_flash_unlock(); |
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while (count >= 32) { |
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if (!stm32h7_flash_write32(addr, b)) { |
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return false; |
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} |
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// check contents |
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if (memcmp((void *)addr, b, 32) != 0) { |
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stm32_flash_lock(); |
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return false; |
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} |
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addr += 32; |
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count -= 32; |
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b += 32; |
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} |
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stm32_flash_lock(); |
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return true; |
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} |
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#else // not STM32H7 |
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bool stm32_flash_write(uint32_t addr, const void *buf, uint32_t count) |
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{ |
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uint8_t *b = (uint8_t *)buf; |
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/* STM32 requires half-word access */ |
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if (count & 1) { |
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return false; |
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} |
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if ((addr+count) >= STM32_FLASH_BASE+STM32_FLASH_SIZE) { |
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return false; |
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} |
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/* Get flash ready and begin flashing */ |
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if (!(RCC->CR & RCC_CR_HSION)) { |
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return false; |
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} |
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#if STM32_FLASH_DISABLE_ISR |
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syssts_t sts = chSysGetStatusAndLockX(); |
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#endif |
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stm32_flash_unlock(); |
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// clear previous errors |
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stm32_flash_clear_errors(); |
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stm32_flash_wait_idle(); |
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// do as much as possible with 32 bit writes |
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while (count >= 4 && (addr & 3) == 0) { |
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FLASH->CR &= ~(FLASH_CR_PSIZE); |
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FLASH->CR |= FLASH_CR_PSIZE_1 | FLASH_CR_PG; |
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const uint32_t v1 = *(uint32_t *)b; |
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putreg32(v1, addr); |
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// ensure write ordering with cache |
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__DSB(); |
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stm32_flash_wait_idle(); |
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const uint32_t v2 = getreg32(addr); |
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if (v2 != v1) { |
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FLASH->CR &= ~(FLASH_CR_PG); |
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goto failed; |
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} |
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count -= 4; |
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b += 4; |
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addr += 4; |
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} |
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// the rest as 16 bit |
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while (count >= 2) { |
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FLASH->CR &= ~(FLASH_CR_PSIZE); |
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FLASH->CR |= FLASH_CR_PSIZE_0 | FLASH_CR_PG; |
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putreg16(*(uint16_t *)b, addr); |
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// ensure write ordering with cache |
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__DSB(); |
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stm32_flash_wait_idle(); |
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if (getreg16(addr) != *(uint16_t *)b) { |
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FLASH->CR &= ~(FLASH_CR_PG); |
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goto failed; |
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} |
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count -= 2; |
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b += 2; |
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addr += 2; |
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} |
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FLASH->CR &= ~(FLASH_CR_PG); |
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stm32_flash_lock(); |
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#if STM32_FLASH_DISABLE_ISR |
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chSysRestoreStatusX(sts); |
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#endif |
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return true; |
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failed: |
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stm32_flash_lock(); |
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#if STM32_FLASH_DISABLE_ISR |
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chSysRestoreStatusX(sts); |
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#endif |
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return false; |
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} |
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#endif // not STM32H7 |
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void stm32_flash_keep_unlocked(bool set) |
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{ |
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if (set && !flash_keep_unlocked) { |
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stm32_flash_unlock(); |
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flash_keep_unlocked = true; |
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} else if (!set && flash_keep_unlocked) { |
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flash_keep_unlocked = false; |
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stm32_flash_lock(); |
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} |
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} |
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#endif // HAL_NO_FLASH_SUPPORT |
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