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325 lines
11 KiB
325 lines
11 KiB
/* |
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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You may obtain a copy of the License at |
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http://www.apache.org/licenses/LICENSE-2.0 |
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Unless required by applicable law or agreed to in writing, software |
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distributed under the License is distributed on an "AS IS" BASIS, |
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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See the License for the specific language governing permissions and |
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limitations under the License. |
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*/ |
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/* |
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header modelled on Nucleo L496ZG header from ChibiOS |
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*/ |
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#ifndef MCUCONF_H |
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#define MCUCONF_H |
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#define STM32L4xx_MCUCONF |
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#define STM32L496_MCUCONF |
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#define STM32L4A6_MCUCONF |
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#if STM32_HSECLK == 0U |
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// no crystal |
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#define STM32_HSE_ENABLED FALSE |
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#define STM32_HSI16_ENABLED TRUE |
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#define STM32_PLLM_VALUE 2 |
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#define STM32_PLLSRC STM32_PLLSRC_HSI16 |
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#elif STM32_HSECLK == 8000000U |
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#define STM32_HSE_ENABLED TRUE |
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#define STM32_HSI16_ENABLED FALSE |
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#define STM32_PLLM_VALUE 1 |
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#define STM32_PLLSRC STM32_PLLSRC_HSE |
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#elif STM32_HSECLK == 12000000U |
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#define STM32_HSE_ENABLED TRUE |
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#define STM32_HSI16_ENABLED FALSE |
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#define STM32_PLLM_VALUE 3 |
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#define STM32_PLLN_VALUE 40 |
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#define STM32_PLLSAI1N_VALUE 24 |
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#define STM32_PLLSAI2N_VALUE 16 |
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#define STM32_PLLSRC STM32_PLLSRC_HSE |
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#elif STM32_HSECLK == 16000000U |
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#define STM32_HSE_ENABLED TRUE |
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#define STM32_HSI16_ENABLED FALSE |
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#define STM32_PLLM_VALUE 2 |
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#define STM32_PLLSRC STM32_PLLSRC_HSE |
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#elif STM32_HSECLK == 24000000U |
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#define STM32_HSE_ENABLED TRUE |
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#define STM32_HSI16_ENABLED FALSE |
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#define STM32_PLLM_VALUE 3 |
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#define STM32_PLLSRC STM32_PLLSRC_HSE |
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#else |
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#error "Unsupported HSE clock" |
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#endif |
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/* |
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* HAL driver system settings. |
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*/ |
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#define STM32_NO_INIT FALSE |
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#define STM32_VOS STM32_VOS_RANGE1 |
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#define STM32_PVD_ENABLE FALSE |
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#define STM32_PLS STM32_PLS_LEV0 |
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#define STM32_HSI48_ENABLED FALSE |
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#define STM32_LSI_ENABLED FALSE |
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#define STM32_LSE_ENABLED FALSE |
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#define STM32_MSIPLL_ENABLED FALSE |
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#define STM32_MSIRANGE STM32_MSIRANGE_4M |
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#define STM32_MSISRANGE STM32_MSISRANGE_4M |
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#define STM32_SW STM32_SW_PLL |
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#ifndef STM32_PLLN_VALUE |
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#define STM32_PLLN_VALUE 20 |
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#endif |
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#define STM32_PLLPDIV_VALUE 0 |
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#define STM32_PLLP_VALUE 7 |
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#define STM32_PLLQ_VALUE 2 |
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#define STM32_PLLR_VALUE 2 |
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#define STM32_HPRE STM32_HPRE_DIV1 |
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#define STM32_PPRE1 STM32_PPRE1_DIV1 |
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#define STM32_PPRE2 STM32_PPRE2_DIV1 |
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#define STM32_STOPWUCK STM32_STOPWUCK_MSI |
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK |
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#define STM32_MCOPRE STM32_MCOPRE_DIV1 |
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK |
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#ifndef STM32_PLLSAI1N_VALUE |
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#define STM32_PLLSAI1N_VALUE 12 |
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#endif |
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#define STM32_PLLSAI1PDIV_VALUE 0 |
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#define STM32_PLLSAI1P_VALUE 7 |
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#define STM32_PLLSAI1Q_VALUE 2 |
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#define STM32_PLLSAI1R_VALUE 2 |
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#ifndef STM32_PLLSAI2N_VALUE |
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#define STM32_PLLSAI2N_VALUE 8 |
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#endif |
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#define STM32_PLLSAI2PDIV_VALUE 0 |
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#define STM32_PLLSAI2P_VALUE 7 |
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#define STM32_PLLSAI2R_VALUE 2 |
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#ifndef STM32_LSECLK |
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#define STM32_LSECLK 32768U |
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#endif |
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#ifndef STM32_LSEDRV |
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#define STM32_LSEDRV (3U << 3U) |
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#endif |
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/* |
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* Peripherals clock sources. |
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*/ |
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK |
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK |
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#define STM32_USART3SEL STM32_USART3SEL_SYSCLK |
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#define STM32_UART4SEL STM32_UART4SEL_SYSCLK |
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#define STM32_UART5SEL STM32_UART5SEL_SYSCLK |
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#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK |
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#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK |
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#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK |
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#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK |
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 |
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 |
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#define STM32_SAI1SEL STM32_SAI1SEL_OFF |
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#define STM32_SAI2SEL STM32_SAI2SEL_OFF |
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 |
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK |
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 |
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2 |
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#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK |
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/* |
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* IRQ system settings. |
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*/ |
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#define STM32_IRQ_EXTI0_PRIORITY 6 |
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#define STM32_IRQ_EXTI1_PRIORITY 6 |
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#define STM32_IRQ_EXTI2_PRIORITY 6 |
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#define STM32_IRQ_EXTI3_PRIORITY 6 |
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#define STM32_IRQ_EXTI4_PRIORITY 6 |
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#define STM32_IRQ_EXTI5_9_PRIORITY 6 |
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#define STM32_IRQ_EXTI10_15_PRIORITY 6 |
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#define STM32_IRQ_EXTI1635_38_PRIORITY 6 |
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#define STM32_IRQ_EXTI18_PRIORITY 6 |
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#define STM32_IRQ_EXTI19_PRIORITY 6 |
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#define STM32_IRQ_EXTI20_PRIORITY 6 |
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#define STM32_IRQ_EXTI21_22_PRIORITY 6 |
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#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 |
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#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 |
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#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 |
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#define STM32_IRQ_TIM1_CC_PRIORITY 7 |
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#define STM32_IRQ_TIM2_PRIORITY 7 |
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#define STM32_IRQ_TIM3_PRIORITY 7 |
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#define STM32_IRQ_TIM4_PRIORITY 7 |
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#define STM32_IRQ_TIM5_PRIORITY 7 |
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#define STM32_IRQ_TIM6_PRIORITY 7 |
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#define STM32_IRQ_TIM7_PRIORITY 7 |
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#define STM32_IRQ_TIM8_UP_PRIORITY 7 |
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#define STM32_IRQ_TIM8_CC_PRIORITY 7 |
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#define STM32_IRQ_USART1_PRIORITY 12 |
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#define STM32_IRQ_USART2_PRIORITY 12 |
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#define STM32_IRQ_USART3_PRIORITY 12 |
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#define STM32_IRQ_UART4_PRIORITY 12 |
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#define STM32_IRQ_UART5_PRIORITY 12 |
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#define STM32_IRQ_LPUART1_PRIORITY 12 |
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/* |
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* ADC driver system settings. |
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*/ |
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#define STM32_ADC_COMPACT_SAMPLES FALSE |
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#ifndef STM32_ADC_USE_ADC1 |
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#define STM32_ADC_USE_ADC1 FALSE |
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#endif |
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#define STM32_ADC_USE_ADC2 FALSE |
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#define STM32_ADC_USE_ADC3 FALSE |
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#define STM32_ADC_ADC1_DMA_PRIORITY 2 |
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#define STM32_ADC_ADC2_DMA_PRIORITY 2 |
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#define STM32_ADC_ADC3_DMA_PRIORITY 2 |
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC3_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
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#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
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#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 |
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/* |
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* CAN driver system settings. |
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*/ |
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#define STM32_CAN_USE_CAN1 FALSE |
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#define STM32_CAN_USE_CAN2 FALSE |
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#define STM32_CAN_CAN1_IRQ_PRIORITY 11 |
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#define STM32_CAN_CAN2_IRQ_PRIORITY 11 |
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/* |
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* DAC driver system settings. |
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*/ |
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#define STM32_DAC_DUAL_MODE FALSE |
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#define STM32_DAC_USE_DAC1_CH1 FALSE |
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#define STM32_DAC_USE_DAC1_CH2 FALSE |
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 |
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 |
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 |
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 |
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/* |
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* I2C driver system settings. |
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*/ |
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#define STM32_I2C_BUSY_TIMEOUT 50 |
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5 |
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5 |
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5 |
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#define STM32_I2C_I2C4_IRQ_PRIORITY 5 |
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#define STM32_I2C_I2C1_DMA_PRIORITY 3 |
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#define STM32_I2C_I2C2_DMA_PRIORITY 3 |
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#define STM32_I2C_I2C3_DMA_PRIORITY 3 |
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#define STM32_I2C_I2C4_DMA_PRIORITY 3 |
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) STM32_DMA_ERROR_HOOK(i2cp) |
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/* |
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* PWM driver system settings. |
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*/ |
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#define STM32_PWM_USE_ADVANCED FALSE |
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/* |
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* RTC driver system settings. |
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*/ |
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#define STM32_RTC_PRESA_VALUE 32 |
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#define STM32_RTC_PRESS_VALUE 1024 |
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#define STM32_RTC_CR_INIT 0 |
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#define STM32_RTC_TAMPCR_INIT 0 |
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/* |
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* SDC driver system settings. |
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*/ |
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#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE |
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#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 |
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#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 |
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#define STM32_SDC_SDMMC_CLOCK_DELAY 10 |
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#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 |
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#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 |
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#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) |
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/* |
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* SERIAL driver system settings. |
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*/ |
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#define STM32_SERIAL_USE_LPUART1 FALSE |
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#define STM32_SERIAL_USART1_PRIORITY 12 |
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#define STM32_SERIAL_USART2_PRIORITY 12 |
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#define STM32_SERIAL_USART3_PRIORITY 12 |
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#define STM32_SERIAL_UART4_PRIORITY 12 |
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#define STM32_SERIAL_UART5_PRIORITY 12 |
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#define STM32_SERIAL_LPUART1_PRIORITY 12 |
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/* |
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* SPI driver system settings. |
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*/ |
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#define STM32_SPI_SPI1_DMA_PRIORITY 1 |
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#define STM32_SPI_SPI2_DMA_PRIORITY 1 |
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#define STM32_SPI_SPI3_DMA_PRIORITY 1 |
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10 |
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10 |
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10 |
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#define STM32_SPI_DMA_ERROR_HOOK(spip) STM32_DMA_ERROR_HOOK(spip) |
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/* |
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* ST driver system settings. |
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*/ |
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#define STM32_ST_IRQ_PRIORITY 8 |
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#ifndef STM32_ST_USE_TIMER |
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#define STM32_ST_USE_TIMER 2 |
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#endif |
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/* |
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* TRNG driver system settings. |
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*/ |
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#define STM32_TRNG_USE_RNG1 FALSE |
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/* |
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* UART driver system settings. |
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*/ |
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#define STM32_UART_USART1_IRQ_PRIORITY 12 |
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#define STM32_UART_USART2_IRQ_PRIORITY 12 |
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#define STM32_UART_USART3_IRQ_PRIORITY 12 |
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#define STM32_UART_UART4_IRQ_PRIORITY 12 |
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#define STM32_UART_UART5_IRQ_PRIORITY 12 |
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#define STM32_UART_USART1_DMA_PRIORITY 0 |
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#define STM32_UART_USART2_DMA_PRIORITY 0 |
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#define STM32_UART_USART3_DMA_PRIORITY 0 |
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#define STM32_UART_UART4_DMA_PRIORITY 0 |
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#define STM32_UART_UART5_DMA_PRIORITY 0 |
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#define STM32_UART_DMA_ERROR_HOOK(uartp) STM32_DMA_ERROR_HOOK(uartp) |
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/* |
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* USB driver system settings. |
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*/ |
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#ifndef STM32_USB_USE_OTG1 |
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#define STM32_USB_USE_OTG1 FALSE |
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#endif |
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#define STM32_USB_OTG1_IRQ_PRIORITY 14 |
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#define STM32_USB_OTG1_RX_FIFO_SIZE 512 |
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/* |
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* WDG driver system settings. |
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*/ |
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#define STM32_WDG_USE_IWDG FALSE |
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/* |
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* WSPI driver system settings. |
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*/ |
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#ifndef STM32_WSPI_USE_QUADSPI1 |
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#define STM32_WSPI_USE_QUADSPI1 FALSE |
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#endif |
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) |
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 |
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// limit ISR count per byte |
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#define STM32_I2C_ISR_LIMIT 6 |
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#endif /* MCUCONF_H */
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