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344 lines
9.9 KiB
344 lines
9.9 KiB
/* |
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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You may obtain a copy of the License at |
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http://www.apache.org/licenses/LICENSE-2.0 |
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Unless required by applicable law or agreed to in writing, software |
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distributed under the License is distributed on an "AS IS" BASIS, |
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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See the License for the specific language governing permissions and |
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limitations under the License. |
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*/ |
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/* |
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this file is included by the board specific ldscript.ld which is |
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generated from hwdef.dat |
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*/ |
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/* RAM region to be used for fast code. */ |
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REGION_ALIAS("FASTCODE_RAM", ram1) |
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/* stack areas are configured to be in AXI RAM (ram1) to ensure the SSBL will load the image */ |
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/* RAM region to be used for Main stack. This stack accommodates the processing |
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of all exceptions and interrupts*/ |
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REGION_ALIAS("MAIN_STACK_RAM", ram1); |
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/* RAM region to be used for the process stack. This is the stack used by |
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the main() function.*/ |
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REGION_ALIAS("PROCESS_STACK_RAM", ram1); |
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/* RAM region to be used for data segment.*/ |
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REGION_ALIAS("DATA_RAM", ram0); |
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/* RAM region to be used for BSS segment.*/ |
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REGION_ALIAS("BSS_RAM", ram0); |
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/* RAM region to be used for the default heap.*/ |
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REGION_ALIAS("HEAP_RAM", ram0); |
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__ram0_start__ = ORIGIN(ram0); |
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__ram0_size__ = LENGTH(ram0); |
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__ram0_end__ = __ram0_start__ + __ram0_size__; |
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/* AXI */ |
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__ram1_start__ = ORIGIN(ram1); |
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__ram1_size__ = LENGTH(ram1); |
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__ram1_end__ = __ram1_start__ + __ram1_size__; |
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/* DTCM */ |
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__ram2_start__ = ORIGIN(ram2); |
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__ram2_size__ = LENGTH(ram2); |
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__ram2_end__ = __ram2_start__ + __ram2_size__; |
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/* ITCM */ |
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__instram_start__ = ORIGIN(instram); |
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__instram_size__ = LENGTH(instram); |
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__instram_end__ = __instram_start__ + __instram_size__; |
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ENTRY(Reset_Handler) |
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SECTIONS |
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{ |
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. = 0; |
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_text = .; |
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startup : ALIGN(16) SUBALIGN(16) |
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{ |
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KEEP(*(.vectors)) |
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} > default_flash |
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constructors : ALIGN(4) SUBALIGN(4) |
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{ |
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__init_array_base__ = .; |
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KEEP(*(SORT(.init_array.*))) |
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KEEP(*(.init_array)) |
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__init_array_end__ = .; |
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} > default_flash |
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destructors : ALIGN(4) SUBALIGN(4) |
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{ |
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__fini_array_base__ = .; |
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KEEP(*(.fini_array)) |
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KEEP(*(SORT(.fini_array.*))) |
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__fini_array_end__ = .; |
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} > default_flash |
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/* INSTRUCTION_RAM area is fast-access ITCM used for RAM-based code, 64k on H7 */ |
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.fastramfunc : ALIGN(4) SUBALIGN(4) |
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{ |
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. = ALIGN(4); |
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__instram_init_text__ = LOADADDR(.fastramfunc); |
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__instram_init__ = .; |
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/* ChibiOS won't boot unless these are excluded */ |
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EXCLUDE_FILE (*vectors.o *crt0_v7m.o *crt1.o) |
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/* performance critical sections of ChibiOS */ |
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*libch.a:ch*.*(.text*) |
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*libch.a:nvic.*(.text*) |
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*libch.a:bouncebuffer.*(.text*) |
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*libch.a:stm32_util.*(.text*) |
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*libch.a:stm32_dma.*(.text*) |
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*libch.a:memstreams.*(.text*) |
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*libch.a:malloc.*(.text*) |
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*libch.a:hrt.*(.text*) |
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*libch.a:hal*.*(.text*) |
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/* a selection of performance critical functions driven CPUInfo results */ |
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lib/lib*.a:Semaphores.*(.text*) |
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lib/lib*.a:AP_Math.*(.text*) |
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lib/lib*.a:vector3.*(.text*) |
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lib/lib*.a:matrix3.*(.text*) |
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/* only used on debug builds */ |
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*libg_nano.a:*memset*(.text*) |
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*libg_nano.a:*memcpy*(.text*) |
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*libm.a:*(.text*) |
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/* For some reason boards won't boot if libc is in RAM, but will with debug on */ |
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/**libc_nano.a:*(.text* .rodata*) |
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*libstdc++_nano.a:(.text* .rodata*)*/ |
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*(.fastramfunc) |
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. = ALIGN(4); |
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__instram_end__ = .; |
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} > instram AT > default_flash |
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/* FLASH_RAM area is primarily used for RAM-based code and data, 256k allocation on H7 */ |
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.ramfunc : ALIGN(4) SUBALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram1_init_text__ = LOADADDR(.ramfunc); |
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__ram1_init__ = .; |
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/* ChibiOS won't boot unless these are excluded */ |
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EXCLUDE_FILE (*vectors.o *crt0_v7m.o *crt1.o) |
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/*libch.a:*(.text* .rodata* .glue_7t .glue_7 .gcc*)*/ |
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/* a selection of larger performance critical functions */ |
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lib/lib*.a:*Filter.*(.text* .rodata*) |
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lib/lib*.a:*Filter2p.*(.text* .rodata*) |
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lib/lib*.a:SPIDevice.*(.text* .rodata*) |
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lib/lib*.a:Util.*(.text* .rodata*) |
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lib/lib*.a:Device.*(.text* .rodata*) |
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lib/lib*.a:Scheduler.*(.text* .rodata*) |
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lib/lib*.a:shared_dma.*(.text* .rodata*) |
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lib/lib*.a:RingBuffer.*(.text* .rodata*) |
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lib/lib*.a:crc.*(.text* .rodata*) |
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lib/lib*.a:matrixN.*(.text* .rodata*) |
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lib/lib*.a:matrix_alg.*(.text* .rodata*) |
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lib/lib*.a:AP_NavEKF*.*(.text* .rodata*) |
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lib/lib*.a:EKFGSF*.*(.text* .rodata*) |
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lib/lib*.a:vector2.*(.text* .rodata*) |
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lib/lib*.a:quaternion.*(.text* .rodata*) |
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lib/lib*.a:polygon.*(.text* .rodata*) |
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lib/lib*.a:flash.*(.text* .rodata*) /* flash ops in RAM so that both banks can be erased */ |
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/* uncomment these to test CPUInfo in FLASH_RAM */ |
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/*Tools/CPUInfo/CPUInfo.*(.text* .rodata*) |
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Tools/CPUInfo/EKF_Maths.*(.text* .rodata*)*/ |
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*(.ramfunc*) |
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. = ALIGN(4); |
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} > ram1 AT > default_flash |
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.ram1 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram1_clear__ = .; |
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. = ALIGN(4); |
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__ram1_noinit__ = .; |
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*(.ram1*) |
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. = ALIGN(4); |
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__ram1_free__ = .; |
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} > ram1 |
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/* DATA_RAM area is DTCM primarily used for RAM-based data, e.g. vtables */ |
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.ramdata : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram2_init_text__ = LOADADDR(.ramdata); |
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__ram2_init__ = .; |
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/* ChibiOS won't boot unless these are excluded */ |
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EXCLUDE_FILE (*vectors.o *crt0_v7m.o *crt1.o) |
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/* performance critical sections of ChibiOS */ |
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*libch.a:ch*.*(.rodata*) |
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*libch.a:nvic.*(.rodata*) |
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*libch.a:bouncebuffer.*(.rodata*) |
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*libch.a:stm32_util.*(.rodata*) |
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*libch.a:stm32_dma.*(.rodata*) |
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*libch.a:memstreams.*(.rodata*) |
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*libch.a:malloc.*(.rodata*) |
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*libch.a:hrt.*(.rodata*) |
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*libch.a:hal*.*(.rodata*) |
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/* a selection of performance critical functions driven CPUInfo results */ |
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lib/lib*.a:Semaphores.*(.rodata*) |
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lib/lib*.a:AP_Math.*(.rodata*) |
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lib/lib*.a:vector3.*(.rodata*) |
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lib/lib*.a:matrix3.*(.rodata*) |
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*libm.a:*(.rodata*) |
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*(.ramdata*) |
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. = ALIGN(4); |
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} > ram2 AT > default_flash |
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.ram2 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram2_clear__ = .; |
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. = ALIGN(4); |
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__ram2_noinit__ = .; |
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*(.ram2*) |
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. = ALIGN(4); |
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__ram2_free__ = .; |
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} > ram2 |
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.text : ALIGN(4) SUBALIGN(4) |
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{ |
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/* we want app_descriptor near the start of flash so a false |
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positive isn't found by the bootloader (eg. ROMFS) */ |
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KEEP(*libch.a:vectors.o); |
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KEEP(*libch.a:crt0_v7m.o); |
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KEEP(*(.app_descriptor)); |
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*(.text) |
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*(.text.*) |
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*(.rodata) |
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*(.rodata.*) |
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*(.glue_7t) |
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*(.glue_7) |
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*(.gcc*) |
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} > default_flash |
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.ARM.extab : |
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{ |
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*(.ARM.extab* .gnu.linkonce.armextab.*) |
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} > default_flash |
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.ARM.exidx : { |
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__exidx_start = .; |
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*(.ARM.exidx* .gnu.linkonce.armexidx.*) |
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__exidx_end = .; |
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} > default_flash |
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.eh_frame_hdr : |
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{ |
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*(.eh_frame_hdr) |
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} > default_flash |
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.eh_frame : ONLY_IF_RO |
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{ |
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*(.eh_frame) |
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} > default_flash |
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.textalign : ONLY_IF_RO |
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{ |
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. = ALIGN(8); |
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} > default_flash |
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/* Legacy symbol, not used anywhere.*/ |
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. = ALIGN(4); |
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PROVIDE(_etext = .); |
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/* Special section for exceptions stack.*/ |
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.mstack : |
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{ |
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. = ALIGN(8); |
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__main_stack_base__ = .; |
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. += __main_stack_size__; |
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. = ALIGN(8); |
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__main_stack_end__ = .; |
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} > MAIN_STACK_RAM |
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/* Special section for process stack.*/ |
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.pstack : |
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{ |
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__process_stack_base__ = .; |
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__main_thread_stack_base__ = .; |
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. += __process_stack_size__; |
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. = ALIGN(8); |
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__process_stack_end__ = .; |
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__main_thread_stack_end__ = .; |
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} > PROCESS_STACK_RAM |
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.data : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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PROVIDE(_textdata = LOADADDR(.data)); |
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PROVIDE(_data = .); |
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__textdata_base__ = LOADADDR(.data); |
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__data_base__ = .; |
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*(.data) |
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*(.data.*) |
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*(.ramtext) |
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. = ALIGN(4); |
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PROVIDE(_edata = .); |
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__data_end__ = .; |
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} > DATA_RAM AT > default_flash |
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.bss (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__bss_base__ = .; |
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*(.bss) |
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*(.bss.*) |
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*(COMMON) |
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. = ALIGN(4); |
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__bss_end__ = .; |
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PROVIDE(end = .); |
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} > BSS_RAM |
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.ram0_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram0_init_text__ = LOADADDR(.ram0_init); |
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__ram0_init__ = .; |
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*(.ram0_init) |
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*(.ram0_init.*) |
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. = ALIGN(4); |
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} > ram0 AT > default_flash |
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.ram0 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram0_clear__ = .; |
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*(.ram0_clear) |
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*(.ram0_clear.*) |
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. = ALIGN(4); |
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__ram0_noinit__ = .; |
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*(.ram0) |
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*(.ram0.*) |
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. = ALIGN(4); |
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__ram0_free__ = .; |
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} > ram0 |
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/* The default heap uses the (statically) unused part of a RAM section.*/ |
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.heap (NOLOAD) : |
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{ |
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. = ALIGN(8); |
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__heap_base__ = .; |
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. = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM); |
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__heap_end__ = .; |
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} > HEAP_RAM |
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/* The crash log uses the unused part of a flash section.*/ |
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.crash_log (NOLOAD) : |
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{ |
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. = ALIGN(32); |
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__crash_log_base__ = .; |
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. = ORIGIN(default_flash) + LENGTH(default_flash); |
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__crash_log_end__ = .; |
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} > default_flash |
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}
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