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30 lines
1.0 KiB
30 lines
1.0 KiB
8 years ago
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diff --git NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
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index 5e2ba73..adda863 100644
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--- NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
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+++ NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
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@@ -95,10 +95,10 @@ static inline void rcc_reset(void)
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putreg32(0x00000000, STM32_RCC_CFGR);
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- /* Reset HSION, HSEON, CSSON and PLLON bits */
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+ /* Reset HSEON, CSSON and PLLON bits */
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regval = getreg32(STM32_RCC_CR);
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- regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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+ regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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putreg32(regval, STM32_RCC_CR);
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/* Reset PLLCFGR register to reset default */
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@@ -619,11 +619,6 @@ static void stm32_stdclockconfig(void)
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volatile int32_t timeout;
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#ifdef STM32_BOARD_USEHSI
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- /* Enable Internal High-Speed Clock (HSI) */
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-
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- regval = getreg32(STM32_RCC_CR);
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- regval |= RCC_CR_HSION; /* Enable HSI */
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- putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSI is ready (or until a timeout elapsed) */
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