You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
359 lines
14 KiB
359 lines
14 KiB
8 years ago
|
/************************************************************************************
|
||
|
|
* nuttx-configs/px4esc-v1/include/board.h
|
||
|
|
*
|
||
|
|
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||
|
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||
|
|
* David Sidrane <david_s5@nscdg.com>
|
||
|
|
*
|
||
|
|
* Redistribution and use in source and binary forms, with or without
|
||
|
|
* modification, are permitted provided that the following conditions
|
||
|
|
* are met:
|
||
|
|
*
|
||
|
|
* 1. Redistributions of source code must retain the above copyright
|
||
|
|
* notice, this list of conditions and the following disclaimer.
|
||
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||
|
|
* notice, this list of conditions and the following disclaimer in
|
||
|
|
* the documentation and/or other materials provided with the
|
||
|
|
* distribution.
|
||
|
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||
|
|
* used to endorse or promote products derived from this software
|
||
|
|
* without specific prior written permission.
|
||
|
|
*
|
||
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||
|
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||
|
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||
|
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||
|
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||
|
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||
|
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||
|
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
||
|
|
*
|
||
|
|
************************************************************************************/
|
||
|
|
|
||
|
|
#ifndef __CONFIGS_PX4ESC_V1_INCLUDE_BOARD_H
|
||
|
|
#define __CONFIGS_PX4ESC_V1_INCLUDE_BOARD_H
|
||
|
|
|
||
|
|
/************************************************************************************
|
||
|
|
* Included Files
|
||
|
|
************************************************************************************/
|
||
|
|
|
||
|
|
#include <nuttx/config.h>
|
||
|
|
|
||
|
|
#ifndef __ASSEMBLY__
|
||
|
|
# include <stdint.h>
|
||
|
|
#endif
|
||
|
|
#include "stm32_rcc.h"
|
||
|
|
#include "stm32_sdio.h"
|
||
|
|
#include "stm32.h"
|
||
|
|
|
||
|
|
/************************************************************************************
|
||
|
|
* Pre-processor Definitions
|
||
|
|
************************************************************************************/
|
||
|
|
|
||
|
|
/* Clocking *************************************************************************/
|
||
|
|
/* The PX4ESC uses a 8MHz crystal connected to the HSE.
|
||
|
|
*
|
||
|
|
* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
|
||
|
|
* System Clock source : PLL (HSE)
|
||
|
|
* SYSCLK(Hz) : 180000000 Determined by PLL configuration
|
||
|
|
* HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE)
|
||
|
|
* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
|
||
|
|
* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
|
||
|
|
* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
|
||
|
|
* HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL)
|
||
|
|
* PLLM : 4 (STM32_PLLCFG_PLLM)
|
||
|
|
* PLLN : 180 (STM32_PLLCFG_PLLN)
|
||
|
|
* PLLP : 2 (STM32_PLLCFG_PLLP)
|
||
|
|
* PLLQ : 2 (STM32_PLLCFG_PPQ)
|
||
|
|
* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
|
||
|
|
* Flash Latency(WS) : 5
|
||
|
|
* Prefetch Buffer : OFF
|
||
|
|
* Instruction cache : ON
|
||
|
|
* Data cache : ON
|
||
|
|
* Require 48MHz for USB OTG FS, : Use PLLSA1M
|
||
|
|
*/
|
||
|
|
|
||
|
|
//TODO(Need to define and add the PLLSAIM );
|
||
|
|
|
||
|
|
/* HSI - 16 MHz RC factory-trimmed
|
||
|
|
* LSI - 32 KHz RC
|
||
|
|
* HSE - On-board crystal frequency is 24MHz
|
||
|
|
* LSE - not installed
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define STM32_BOARD_XTAL 8000000ul
|
||
|
|
|
||
|
|
#define STM32_HSI_FREQUENCY 16000000ul
|
||
|
|
#define STM32_LSI_FREQUENCY 32000
|
||
|
|
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||
|
|
|
||
|
|
/* Main PLL Configuration.
|
||
|
|
*
|
||
|
|
* PLL source is HSE
|
||
|
|
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
|
||
|
|
* = (8,000,000 / 4) * 180
|
||
|
|
* = 360,000,000
|
||
|
|
* SYSCLK = PLL_VCO / PLLP
|
||
|
|
* = 360,000,000/ 2 = 180,000,000
|
||
|
|
* USB OTG FS will use PLLSA1M
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
//
|
||
|
|
|
||
|
|
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
|
||
|
|
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(180)
|
||
|
|
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||
|
|
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
|
||
|
|
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||
|
|
|
||
|
|
/* Configure factors for PLLSAI clock */
|
||
|
|
|
||
|
|
#define STM32_RCC_PLLSAICFGR_PLLSAIM RCC_PLLSAICFGR_PLLSAIM(4)
|
||
|
|
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(96)
|
||
|
|
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(4)
|
||
|
|
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
|
||
|
|
|
||
|
|
/* Configure Dedicated Clock Configuration Register */
|
||
|
|
|
||
|
|
#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1)
|
||
|
|
#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1)
|
||
|
|
#define STM32_RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_PLLSAI
|
||
|
|
#define STM32_RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_PLLSAI
|
||
|
|
#define STM32_RCC_DCKCFGR_TIMPRE 0
|
||
|
|
#define STM32_RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_SAI1SRC_PLL
|
||
|
|
#define STM32_RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_SAI2SRC_PLL
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/* Configure factors for PLLI2S clock */
|
||
|
|
|
||
|
|
|
||
|
|
#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
|
||
|
|
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||
|
|
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
|
||
|
|
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
|
||
|
|
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
|
||
|
|
|
||
|
|
/* Configure Dedicated Clock Configuration Register 2 */
|
||
|
|
|
||
|
|
#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
|
||
|
|
#define STM32_RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_HSI
|
||
|
|
#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLLSAI
|
||
|
|
#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
|
||
|
|
#define STM32_RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_PLL
|
||
|
|
|
||
|
|
#define STM32_SYSCLK_FREQUENCY 180000000ul
|
||
|
|
|
||
|
|
/* AHB clock (HCLK) is SYSCLK (180MHz) */
|
||
|
|
|
||
|
|
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||
|
|
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||
|
|
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||
|
|
|
||
|
|
/* APB1 clock (PCLK1) is HCLK/4 (45MHz) */
|
||
|
|
|
||
|
|
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||
|
|
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||
|
|
|
||
|
|
/* Timers driven from APB1 will be twice PCLK1 */
|
||
|
|
|
||
|
|
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||
|
|
|
||
|
|
/* APB2 clock (PCLK2) is HCLK/2 (90MHz) */
|
||
|
|
|
||
|
|
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||
|
|
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||
|
|
|
||
|
|
/* Timers driven from APB2 will be twice PCLK2 */
|
||
|
|
|
||
|
|
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||
|
|
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||
|
|
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||
|
|
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||
|
|
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||
|
|
|
||
|
|
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
||
|
|
* otherwise frequency is 2xAPBx.
|
||
|
|
* Note: TIM1,8-11 are on APB2, others on APB1
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||
|
|
#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||
|
|
#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||
|
|
#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||
|
|
#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN
|
||
|
|
#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||
|
|
#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN
|
||
|
|
#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||
|
|
#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN
|
||
|
|
#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN
|
||
|
|
#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN
|
||
|
|
#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN
|
||
|
|
#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN
|
||
|
|
#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN
|
||
|
|
|
||
|
|
/* Leds *************************************************************************/
|
||
|
|
|
||
|
|
/* LED index values for use with board_setled() */
|
||
|
|
|
||
|
|
#define BOARD_LED1 0
|
||
|
|
#define BOARD_LED_RED BOARD_LED1
|
||
|
|
#define BOARD_LED2 1
|
||
|
|
#define BOARD_LED_GREEN BOARD_LED2
|
||
|
|
#define BOARD_LED3 2
|
||
|
|
#define BOARD_LED_BLUE BOARD_LED3
|
||
|
|
#define BOARD_NLEDS 3
|
||
|
|
|
||
|
|
/* LED bits for use with board_setleds() */
|
||
|
|
|
||
|
|
#define BOARD_LED_RED_BIT (1 << BOARD_LED_RED)
|
||
|
|
#define BOARD_LED_GREEN_BIT (1 << BOARD_LED_GREEN)
|
||
|
|
#define BOARD_LED_BLUE_BIT (1 << BOARD_LED_BLUE)
|
||
|
|
|
||
|
|
/* TODO:define these
|
||
|
|
* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
|
||
|
|
*
|
||
|
|
* defined. In that case, the usage by the board port is as follows:
|
||
|
|
*
|
||
|
|
* SYMBOL Meaning LED state
|
||
|
|
* Red Green Blue
|
||
|
|
* ------------------------ -------------------------- ------ ------ ----*/
|
||
|
|
|
||
|
|
#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
|
||
|
|
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
|
||
|
|
#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
|
||
|
|
#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
|
||
|
|
#define LED_INIRQ 4 /* In an interrupt N/C GLOW N/C */
|
||
|
|
#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
|
||
|
|
#define LED_ASSERTION 6 /* An assertion failed GLOW GLOW N/C */
|
||
|
|
#define LED_PANIC 7 /* The system has crashed Blk OFF N/C */
|
||
|
|
#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Thus if the blue is statically on, NuttX has successfully booted and is,
|
||
|
|
* apparently, running normally. If the Red LED is flashing at
|
||
|
|
* approximately 2Hz, then a fatal error has been detected and the system
|
||
|
|
* has halted.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/* Alternate function pin selections ************************************************/
|
||
|
|
|
||
|
|
/* UARTs */
|
||
|
|
|
||
|
|
#define GPIO_USART3_RX GPIO_USART3_RX_4
|
||
|
|
#define GPIO_USART3_TX GPIO_USART3_TX_1
|
||
|
|
|
||
|
|
/* CAN
|
||
|
|
*
|
||
|
|
* CAN1 is routed to the onboard transceiver.
|
||
|
|
* CAN2 is routed to the onboard transceiver.
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define GPIO_CAN1_RX GPIO_CAN1_RX_2
|
||
|
|
#define GPIO_CAN1_TX GPIO_CAN1_TX_2
|
||
|
|
#define GPIO_CAN2_RX GPIO_CAN2_RX_2
|
||
|
|
#define GPIO_CAN2_TX GPIO_CAN2_TX_2
|
||
|
|
|
||
|
|
/* TIMERS */
|
||
|
|
|
||
|
|
#define GPIO_TIM3_CH2OUT GPIO_TIM3_CH2OUT_3
|
||
|
|
#define GPIO_TIM3_CH3OUT GPIO_TIM3_CH3OUT_2
|
||
|
|
#define GPIO_TIM3_CH4OUT GPIO_TIM3_CH4OUT_2
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(CONFIG_BOARD_USE_PROBES)
|
||
|
|
# define PROBE_N(n) (1<<((n)-1))
|
||
|
|
# define PROBE_1 GPIO_TEST1
|
||
|
|
# define PROBE_2 GPIO_TEST2
|
||
|
|
# define PROBE_3 GPIO_TEST3
|
||
|
|
# define PROBE_3 GPIO_TEST4
|
||
|
|
|
||
|
|
# define PROBE_INIT(mask) \
|
||
|
|
do { \
|
||
|
|
if ((mask)& PROBE_N(1)) { stm32_configgpio(PROBE_1); } \
|
||
|
|
if ((mask)& PROBE_N(2)) { stm32_configgpio(PROBE_2); } \
|
||
|
|
if ((mask)& PROBE_N(3)) { stm32_configgpio(PROBE_3); } \
|
||
|
|
} while(0)
|
||
|
|
|
||
|
|
# define PROBE(n,s) do {stm32_gpiowrite(PROBE_##n,(s));}while(0)
|
||
|
|
# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true)
|
||
|
|
#else
|
||
|
|
# define PROBE_INIT(mask)
|
||
|
|
# define PROBE(n,s)
|
||
|
|
# define PROBE_MARK(n)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/************************************************************************************
|
||
|
|
* Public Data
|
||
|
|
************************************************************************************/
|
||
|
|
|
||
|
|
#ifndef __ASSEMBLY__
|
||
|
|
|
||
|
|
#undef EXTERN
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
#define EXTERN extern "C"
|
||
|
|
extern "C"
|
||
|
|
{
|
||
|
|
#else
|
||
|
|
#define EXTERN extern
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/************************************************************************************
|
||
|
|
* Public Function Prototypes
|
||
|
|
************************************************************************************/
|
||
|
|
/************************************************************************************
|
||
|
|
* Name: stm32_boardinitialize
|
||
|
|
*
|
||
|
|
* Description:
|
||
|
|
* All STM32 architectures must provide the following entry point. This entry point
|
||
|
|
* is called early in the initialization -- after all memory has been configured
|
||
|
|
* and mapped but before any devices have been initialized.
|
||
|
|
*
|
||
|
|
************************************************************************************/
|
||
|
|
|
||
|
|
void stm32_boardinitialize(void);
|
||
|
|
|
||
|
|
/************************************************************************************
|
||
|
|
* Name: stm32_ledinit, stm32_setled, and stm32_setleds
|
||
|
|
*
|
||
|
|
* Description:
|
||
|
|
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If
|
||
|
|
* CONFIG_ARCH_LEDS is not defined, then the following interfaces are available to
|
||
|
|
* control the LEDs from user applications.
|
||
|
|
*
|
||
|
|
************************************************************************************/
|
||
|
|
|
||
|
|
#ifndef CONFIG_ARCH_LEDS
|
||
|
|
void stm32_led_initialize(void);
|
||
|
|
void stm32_setled(int led, bool ledon);
|
||
|
|
void stm32_setleds(uint8_t ledset);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if !defined(CONFIG_NSH_LIBRARY)
|
||
|
|
int app_archinitialize(void);
|
||
|
|
#else
|
||
|
|
#define app_archinitialize() (-ENOSYS)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#undef EXTERN
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __ASSEMBLY__ */
|
||
|
|
#endif /* __CONFIGS_PX4ESC_V1_INCLUDE_BOARD_H */
|