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/************************************************************************************
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* configs/tap-v1/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2012-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIG_TAP_V1_INCLUDE_BOARD_H
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#define __CONFIG_TAP_V1_INCLUDE_BOARD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include "stm32_rcc.h"
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#include "stm32.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The TAP V1 uses a 16MHz crystal connected to the HSE.
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*
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* This is the canonical configuration:
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 16000000 (STM32_BOARD_XTAL)
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* PLLM : 8 (STM32_PLLCFG_PLLM)
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* PLLN : 168 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 7 (STM32_PLLCFG_PLLQ)
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
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* Flash Latency(WS) : 5
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 16MHz
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* LSE - not installed
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*/
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#define STM32_BOARD_XTAL 16000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (16,000,000 / 8) * 168
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* = 336,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 336,000,000 / 2 = 168,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 336,000,000 / 7
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* = 48,000,000
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(168)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
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#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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/* LED definitions ******************************************************************/
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
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* way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with stm32_setled()
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*
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* PC4 BLUE_LED D4 Blue LED cathode
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* PC5 RED_LED D5 Red LED cathode
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*/
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_NLEDS 2
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#define BOARD_LED_BLUE BOARD_LED1
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#define BOARD_LED_RED BOARD_LED2
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/* LED bits for use with stm32_setleds() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on board
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* the tap-v1. The following definitions describe how NuttX controls
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* the LEDs:
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*/
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#define LED_STARTED 0 /* BLUE */
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#define LED_HEAPALLOCATE 1 /* LED2 */
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#define LED_IRQSENABLED 2 /* BLUE */
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#define LED_STACKCREATED 3 /* BLUE + RED */
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#define LED_INIRQ 4 /* BLUE */
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#define LED_SIGNAL 5 /* RED */
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#define LED_ASSERTION 6 /* BLUE + RED */
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#define LED_PANIC 7 /* BLUE + RED */
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/* Alternate function pin selections ************************************************/
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/*
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* USARTs.
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*
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*
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* Peripheral Port Signal Name CONN
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* USART1_TX PB6 GPS_USART1_TX JP1-15,16
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* USART1_RX PB7 GPS_USART1_RX JP1-13,14
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* USART2_TX PA2 GB_USART2_TX JP2-19,20
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* USART2_RX PA3 GB_USART2_RX JP2-21,22
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* USART3_TX PC10 RF2_USART3_TX J3-2
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* USART3_RX PC11 RF2_USART3_RX J3-1
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* USART6_TX PC6 RF_USART6_TX JP2-15,16
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* USART6_RX PC7 RF_USART6_RX JP2-17,18
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*/
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#define GPIO_USART1_TX GPIO_USART1_TX_2
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#define GPIO_USART1_RX GPIO_USART1_RX_2
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#define GPIO_USART2_TX GPIO_USART2_TX_1
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#define GPIO_USART2_RX GPIO_USART2_RX_1
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#define GPIO_USART3_TX GPIO_USART3_TX_2
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#define GPIO_USART3_RX GPIO_USART3_RX_2
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#define GPIO_USART6_TX GPIO_USART6_TX_1
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#define GPIO_USART6_RX GPIO_USART6_RX_1
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#define GPIO_UART7_TX GPIO_UART7_TX_1
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#define GPIO_UART7_RX GPIO_UART7_RX_1
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/* USART DMA configuration for USART 1 and 6 */
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#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
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/*
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* UARTs.
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*
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* N.B. The 's' is here to match the wrong labeling on Schematic
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*
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* Peripheral Port Signal Name CONN
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* UART4_TX PA0 OFS_UsART4_TX JP1-19,20
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* UART4_RX PA1 OFS_UsART4_RX JP1-17,18
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* UART5_TX PC12 ESC_UsART5_TX U7-HCT244 etal ESC
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* UART5_RX PD2 ESC_UsART5_RX U8-5 74HCT151
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*
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* Note that UART5 has no optional pinout, so it is not listed here.
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*
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*/
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#define GPIO_UART4_TX GPIO_UART4_TX_1
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#define GPIO_UART4_RX GPIO_UART4_RX_1
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/*
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* I2C
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*
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* Peripheral Port Signal Name CONN
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* I2C1_SDA PB9 I2C1_SDA J2-4,9,16,21 mpu6050, U4 MS6507
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* I2C1_SDL PB8 I2C1_SCL J2-3,10,15,22 mpu6050, U4 MS6507
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* I2C2_SDA PB11 Sonar Echo/I2C_SDA JP2-31,32
|
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|
|
* I2C2_SDL PB10 Sonar Trig/I2C_SCL JP2-29,30
|
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|
|
* I2C3_SDA PC9 COMPASS_I2C3_SDA JP1-27,28
|
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|
* I2C3_SDL PA8 COMPASS_I2C3_SCL JP1-25,26
|
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|
|
*
|
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|
|
* The optional _GPIO configurations allow the I2C driver to manually
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|
|
* reset the bus to clear stuck slaves. They match the pin configuration,
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|
|
* but are normally-high GPIOs.
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|
|
*/
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|
|
// #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
|
|
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|
|
// #define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
|
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|
|
// #define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
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|
|
// #define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8)
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|
// #define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
|
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|
|
// #define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
|
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|
|
// #define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
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|
|
// #define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
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|
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
|
|
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|
|
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
|
|
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|
|
#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN9)
|
|
|
|
|
#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN8)
|
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|
/*
|
|
|
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* SPI
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*
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* Peripheral Port Signal Name CONN
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* SPI2_NSS PB12 SD_SPI2_NSS SD-2 CS
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* TBD
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*
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*/
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#define GPIO_SPI3_NSS (GPIO_SPI3_NSS_1 | GPIO_SPEED_50MHz)
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#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2 | GPIO_SPEED_50MHz)
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#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1 | GPIO_SPEED_50MHz)
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#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1 | GPIO_SPEED_50MHz)
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#define GPIO_SPI4_NSS (GPIO_SPI4_NSS_1 | GPIO_SPEED_50MHz)
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#define GPIO_SPI4_SCK (GPIO_SPI4_SCK_2 | GPIO_SPEED_50MHz)
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#define GPIO_SPI4_MISO (GPIO_SPI4_MISO_1 | GPIO_SPEED_50MHz)
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#define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_1 | GPIO_SPEED_50MHz)
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/* The following Pin Mapping is just for completeness */
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/*
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* JTAG
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*
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* We will only enable SW-DP, JTAG-DP will be disabled
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*
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* Function Port Signal Name CONN
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* SWDIO PA13 DAT J10-3,J7
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* SWCLK PA14 CLK J10-4,J8
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*
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*/
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/*
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* BOOT
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*
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* Function Port Signal Name CONN
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* BOOT0 NA BOOT0 GND via 10 K
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* BOOT1 PB2 BOOT1 V3.3 - 10 K
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*
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* As jumpered the device can only boot from FLASH.
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*
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* It can be booted to:
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*
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* SRAM if BOOT0 is pulled High with 1K.
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* System memory if:
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* BOOT0 is pulled High with 1K and
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* BOOT1 is pulled Low with 1K
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*/
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/*
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* Timer PWM
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*
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* Peripheral Port Signal Name CONN
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* TIM3_CH1 PA6 LED_R JP2-23,24
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* TIM3_CH2 PA7 LED_G JP2-25,26
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* TIM3_CH3 PB0 LED_B JP2-27,28
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* TIM3_CH4 PB1 nPWM_1 AUX1(Landing Gear) JP1-21,22
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*/
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/*
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* GPIO
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*
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* Port Signal Name CONN
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* PA4 POWER JP1-23, - Must be held High to run w/o USB
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* PB4 TEMP_CONT J2-2,11,14,23 - Gyro Heater
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* PC0 VOLTAGE JP2-13,14 - 1.84 @16.66 1.67 @15.12 Scale 0.1105
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* PC1 KEY_AD JP1-31,32 - Low when Power button is depressed
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* PC2 SD_SW SD-9 SW - Card Present
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* PC3 PCON_RADIO JP1-29,30
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* PC13 S2 U8-9 74HCT151
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* PC14 S1 U8-10 74HCT151
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* PC15 S0 U8-11 74HCT151
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*/
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/*
|
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* USB
|
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*
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* Port Signal Name CONN
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* PA9 OTG_FS_VBUS J1-1
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* PA10 OTG_FS_ID J1-4
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* PA11 OTG_FS_DM J1-2
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* PA12 OTG_FS_DP J1-3
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*/
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/*
|
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|
|
* UNUSED PINS - In an idle world - these would have been tied to pads to
|
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|
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* facilitate debugging probs.
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|
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* Port
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|
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* PA15
|
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|
|
* PB3
|
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|
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* PB5
|
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|
|
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* PC8
|
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|
|
*/
|
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|
|
/* Board provides GPIO or other Hardware for signaling to timing analyzer */
|
|
|
|
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|
|
#if defined(CONFIG_BOARD_USE_PROBES)
|
|
|
|
|
# define PROBE_N(n) (1<<((n)-1))
|
|
|
|
|
# define PROBE_1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN15)
|
|
|
|
|
# define PROBE_2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN3)
|
|
|
|
|
# define PROBE_3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN5)
|
|
|
|
|
# define PROBE_4 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN8)
|
|
|
|
|
|
|
|
|
|
# define PROBE_INIT(mask) \
|
|
|
|
|
do { \
|
|
|
|
|
if ((mask)& PROBE_N(1)) { stm32_configgpio(PROBE_1); } \
|
|
|
|
|
if ((mask)& PROBE_N(2)) { stm32_configgpio(PROBE_2); } \
|
|
|
|
|
if ((mask)& PROBE_N(3)) { stm32_configgpio(PROBE_3); } \
|
|
|
|
|
if ((mask)& PROBE_N(4)) { stm32_configgpio(PROBE_4); } \
|
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
|
|
# define PROBE(n,s) do {stm32_gpiowrite(PROBE_##n,(s));}while(0)
|
|
|
|
|
# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true)
|
|
|
|
|
#else
|
|
|
|
|
# define PROBE_INIT(mask)
|
|
|
|
|
# define PROBE(n,s)
|
|
|
|
|
# define PROBE_MARK(n)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Public Data
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
|
#if defined(__cplusplus)
|
|
|
|
|
#define EXTERN extern "C"
|
|
|
|
|
extern "C" {
|
|
|
|
|
#else
|
|
|
|
|
#define EXTERN extern
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Public Function Prototypes
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: stm32_boardinitialize
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
|
|
|
|
* All STM32 architectures must provide the following entry point. This entry point
|
|
|
|
|
* is called early in the initialization -- after all memory has been configured
|
|
|
|
|
* and mapped but before any devices have been initialized.
|
|
|
|
|
*
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
EXTERN void stm32_boardinitialize(void);
|
|
|
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
|
#if defined(__cplusplus)
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
#endif /* __CONFIG_TAP_V1_INCLUDE_BOARD_H */
|
