/************************************************************************************
* configs / aerocore / include / board . h
* include / arch / board / board . h
*
* Copyright ( C ) 2009 Gregory Nutt . All rights reserved .
* Author : Gregory Nutt < gnutt @ nuttx . org >
*
* Redistribution and use in source and binary forms , with or without
* modification , are permitted provided that the following conditions
* are met :
*
* 1. Redistributions of source code must retain the above copyright
* notice , this list of conditions and the following disclaimer .
* 2. Redistributions in binary form must reproduce the above copyright
* notice , this list of conditions and the following disclaimer in
* the documentation and / or other materials provided with the
* distribution .
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission .
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES , INCLUDING , BUT NOT
* LIMITED TO , THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED . IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT , INDIRECT ,
* INCIDENTAL , SPECIAL , EXEMPLARY , OR CONSEQUENTIAL DAMAGES ( INCLUDING ,
* BUT NOT LIMITED TO , PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES ; LOSS
* OF USE , DATA , OR PROFITS ; OR BUSINESS INTERRUPTION ) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY , WHETHER IN CONTRACT , STRICT
* LIABILITY , OR TORT ( INCLUDING NEGLIGENCE OR OTHERWISE ) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE , EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE .
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# ifndef __ARCH_BOARD_BOARD_H
# define __ARCH_BOARD_BOARD_H
/************************************************************************************
* Included Files
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# include <nuttx/config.h>
# ifndef __ASSEMBLY__
# include <stdint.h>
# endif
# include <stm32.h>
/************************************************************************************
* Definitions
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* Clocking *************************************************************************/
/* The AeroCore uses a 24MHz crystal connected to the HSE.
*
* This is the " standard " configuration as set up by arch / arm / src / stm32f40xx_rcc . c :
* System Clock source : PLL ( HSE )
* SYSCLK ( Hz ) : 168000000 Determined by PLL configuration
* HCLK ( Hz ) : 168000000 ( STM32_RCC_CFGR_HPRE )
* AHB Prescaler : 1 ( STM32_RCC_CFGR_HPRE )
* APB1 Prescaler : 4 ( STM32_RCC_CFGR_PPRE1 )
* APB2 Prescaler : 2 ( STM32_RCC_CFGR_PPRE2 )
* HSE Frequency ( Hz ) : 24000000 ( STM32_BOARD_XTAL )
* PLLM : 24 ( STM32_PLLCFG_PLLM )
* PLLN : 336 ( STM32_PLLCFG_PLLN )
* PLLP : 2 ( STM32_PLLCFG_PLLP )
* PLLQ : 7 ( STM32_PLLCFG_PPQ )
* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
* Flash Latency ( WS ) : 5
* Prefetch Buffer : OFF
* Instruction cache : ON
* Data cache : ON
* Require 48 MHz for USB OTG FS , : Enabled
* SDIO and RNG clock
*/
/* HSI - 16 MHz RC factory-trimmed
* LSI - 32 KHz RC
* HSE - On - board crystal frequency is 24 MHz
* LSE - not installed
*/
# define STM32_BOARD_XTAL 24000000ul
# define STM32_HSI_FREQUENCY 16000000ul
# define STM32_LSI_FREQUENCY 32000
# define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
/* Main PLL Configuration.
*
* PLL source is HSE
* PLL_VCO = ( STM32_HSE_FREQUENCY / PLLM ) * PLLN
* = ( 24 , 000 , 000 / 24 ) * 336
* = 336 , 000 , 000
* SYSCLK = PLL_VCO / PLLP
* = 336 , 000 , 000 / 2 = 168 , 000 , 000
* USB OTG FS , SDIO and RNG Clock
* = PLL_VCO / PLLQ
* = 48 , 000 , 000
*/
# define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(24)
# define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
# define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
# define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
# define STM32_SYSCLK_FREQUENCY 168000000ul
/* AHB clock (HCLK) is SYSCLK (168MHz) */
# define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
# define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
# define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
# define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
# define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
/* Timers driven from APB1 will be twice PCLK1 */
# define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
# define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
# define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
# define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
# define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
# define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
# define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
# define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
# define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
# define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
# define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
/* Timers driven from APB2 will be twice PCLK2 */
# define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
# define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
# define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
# define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
# define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2 xAPBx .
* Note : TIM1 , 8 are on APB2 , others on APB1
*/
# define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
# define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
/* Alternate function pin selections ************************************************/
/*
* UARTs .
*/
/* USART1 on PB[6,7]: GPS */
# define GPIO_USART1_RX GPIO_USART1_RX_2
# define GPIO_USART1_TX GPIO_USART1_TX_2
/* USART2 on PD[5,6]: J5 Breakout */
# define GPIO_USART2_RX GPIO_USART2_RX_2
# define GPIO_USART2_TX GPIO_USART2_TX_2
# define GPIO_USART2_CTS 0 // unused
# define GPIO_USART2_RTS 0 // unused
/* USART3 on PD[8,9]: to DuoVero UART2 */
# define GPIO_USART3_RX GPIO_USART3_RX_3
# define GPIO_USART3_TX GPIO_USART3_TX_3
# define GPIO_USART3_CTS 0 // unused
# define GPIO_USART3_RTS 0 // unused
/* UART7 on PE[78]: J7 Breakout */
# define GPIO_UART7_RX GPIO_UART7_RX_1
# define GPIO_UART7_TX GPIO_UART7_TX_1
/*
* UART8 on PE [ 0 - 1 ] : System Console on Port C of USB ( J7 )
* No alternate pin config
*/
/* USART[1,6] require a RX DMA configuration */
# define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
# define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
/*
* I2C
*
* The optional _GPIO configurations allow the I2C driver to manually
* reset the bus to clear stuck slaves . They match the pin configuration ,
* but are normally - high GPIOs .
*/
/* PB[10-11]: I2C2 is broken out on J9 header */
# define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
# define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
# define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
# define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
/*
* SPI
*/
/* PA[4-7] SPI1 broken out on J12 */
# define GPIO_SPI1_NSS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) /* should be GPIO_SPI1_NSS_2 but use as a GPIO */
# define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz)
# define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz)
# define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz)
/* PB[12-15]: SPI2 connected to DuoVero SPI1 */
# define GPIO_SPI2_NSS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) /* should be GPIO_SPI2_NSS_2 but use as a GPIO */
# define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz)
# define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz)
# define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz)
/* PC[10-12]: SPI3 connected to onboard sensors */
# define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz)
# define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz)
# define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz)
/* PE[11-14]: SPI4 connected to FRAM */
# define GPIO_SPI4_NSS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN11) /* should be GPIO_SPI4_NSS_2 but use as a GPIO */
# define GPIO_SPI4_SCK (GPIO_SPI4_SCK_2|GPIO_SPEED_50MHz)
# define GPIO_SPI4_MISO (GPIO_SPI4_MISO_2|GPIO_SPEED_50MHz)
# define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_2|GPIO_SPEED_50MHz)
/************************************************************************************
* Public Data
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# ifndef __ASSEMBLY__
# undef EXTERN
# if defined(__cplusplus)
# define EXTERN extern "C"
extern " C " {
# else
# define EXTERN extern
# endif
/************************************************************************************
* Public Function Prototypes
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/************************************************************************************
* Name : stm32_boardinitialize
*
* Description :
* All STM32 architectures must provide the following entry point . This entry point
* is called early in the intitialization - - after all memory has been configured
* and mapped but before any devices have been initialized .
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
EXTERN void stm32_boardinitialize ( void ) ;
# undef EXTERN
# if defined(__cplusplus)
}
# endif
# endif /* __ASSEMBLY__ */
# endif /* __ARCH_BOARD_BOARD_H */
