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@ -224,7 +224,7 @@ int px4_arch_adc_init(uint32_t base_address)
@@ -224,7 +224,7 @@ int px4_arch_adc_init(uint32_t base_address)
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} |
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/* arbitrarily configure all channels for 810.5 cycle sample time */ |
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/* arbitrarily configure all channels for 64.5 cycle sample time */ |
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rSMPR1(base_address) = ADC_SMPR1_DEFAULT; |
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rSMPR2(base_address) = ADC_SMPR2_DEFAULT; |
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@ -260,6 +260,10 @@ int px4_arch_adc_init(uint32_t base_address)
@@ -260,6 +260,10 @@ int px4_arch_adc_init(uint32_t base_address)
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} |
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} |
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/* Read out result, clear EOC */ |
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(void) rDR(base_address); |
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return OK; |
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} |
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@ -278,7 +282,7 @@ uint32_t px4_arch_adc_sample(uint32_t base_address, unsigned channel)
@@ -278,7 +282,7 @@ uint32_t px4_arch_adc_sample(uint32_t base_address, unsigned channel)
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rISR(base_address) &= ~ADC_INT_EOC; |
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} |
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/* run a single conversion right now - should take about 810.5 cycles (34 microseconds) max */ |
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/* run a single conversion right now - should take about 64.5 cycles (34 microseconds) max */ |
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rPCSEL(base_address) |= 1 << channel; |
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rSQR1(base_address) = channel << ADC_SQR1_SQ_OFFSET; |
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