From 1bf0218c87f7d1d1ba214e99b41ed87d93dea5d4 Mon Sep 17 00:00:00 2001 From: Daniel Agar Date: Sun, 4 Oct 2020 14:57:12 -0400 Subject: [PATCH] boards: mRo Control Zero F7 fix RC input and cleanup sensors init --- boards/mro/ctrl-zero-f7/init/rc.board_sensors | 10 ++-- .../ctrl-zero-f7/nuttx-config/include/board.h | 49 ++----------------- .../nuttx-config/include/board_dma_map.h | 8 +-- .../nuttx-config/scripts/script.ld | 16 +++--- boards/mro/ctrl-zero-f7/src/board_config.h | 34 +++++-------- boards/mro/ctrl-zero-f7/src/init.c | 11 +---- boards/mro/ctrl-zero-f7/src/spi.cpp | 2 +- 7 files changed, 37 insertions(+), 93 deletions(-) diff --git a/boards/mro/ctrl-zero-f7/init/rc.board_sensors b/boards/mro/ctrl-zero-f7/init/rc.board_sensors index 79d2b3bacc..88205f4ec8 100644 --- a/boards/mro/ctrl-zero-f7/init/rc.board_sensors +++ b/boards/mro/ctrl-zero-f7/init/rc.board_sensors @@ -6,14 +6,14 @@ board_adc start # Internal ICM-20602 -icm20602 -s -R 8 start +icm20602 -s -b 1 -R 8 start # Internal SPI bus BMI088 accel & gyro -bmi088 -A -R 8 -s start -bmi088 -G -R 8 -s start +bmi088 -A -s -b 5 -R 8 start +bmi088 -G -s -b 5 -R 8 start # Internal ICM-20948 (with magnetometer) -icm20948 -s -R 8 -M start +icm20948 -s -b 1 -R 8 -M start # Interal DPS310 (barometer) -dps310 -s start +dps310 -s -b 2 start diff --git a/boards/mro/ctrl-zero-f7/nuttx-config/include/board.h b/boards/mro/ctrl-zero-f7/nuttx-config/include/board.h index c117936312..47ba227f23 100644 --- a/boards/mro/ctrl-zero-f7/nuttx-config/include/board.h +++ b/boards/mro/ctrl-zero-f7/nuttx-config/include/board.h @@ -63,7 +63,6 @@ * HSI: 16 MHz RC factory-trimmed * HSE: 24 MHz crystal for HSE */ - #define STM32_BOARD_XTAL 24000000ul #define STM32_HSI_FREQUENCY 16000000ul @@ -102,7 +101,6 @@ * SYSCLK = 432 MHz / 2 = 216 MHz * SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz */ - #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(24) #define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432) #define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 @@ -113,7 +111,6 @@ #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9) /* Configure factors for PLLSAI clock */ - #define CONFIG_STM32F7_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) @@ -121,7 +118,6 @@ #define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) /* Configure Dedicated Clock Configuration Register */ - #define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) #define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1) #define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0) @@ -131,10 +127,7 @@ #define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 #define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 - - /* Configure factors for PLLI2S clock */ - #define CONFIG_STM32F7_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) @@ -142,7 +135,6 @@ #define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) /* Configure Dedicated Clock Configuration Register 2 */ - #define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB #define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB #define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB @@ -170,18 +162,15 @@ */ /* AHB clock (HCLK) is SYSCLK (216 MHz) */ - #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */ - #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* Timers driven from APB1 will be twice PCLK1 */ - #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -193,12 +182,10 @@ #define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ - #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* Timers driven from APB2 will be twice PCLK2 */ - #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) @@ -216,7 +203,6 @@ /* Use the Falling edge of the SDIO_CLK clock to change the edge the * data and commands are change on */ - #define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE #define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) @@ -234,8 +220,6 @@ /* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz */ -//TODO #warning "Check Freq for 24mHz" - #ifdef CONFIG_STM32F7_SDMMC_DMA # define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #else @@ -256,8 +240,8 @@ #define BOARD_FLASH_WAITSTATES 7 -/* Alternate function pin selections ************************************************/ +/* UART/USART */ #define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */ #define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */ #define GPIO_USART2_RTS GPIO_USART2_RTS_2 /* PD4 */ @@ -283,20 +267,13 @@ * GPIO_UART8_TX PE1 */ -/* CAN - * - * CAN1 is routed to transceiver. - */ + +/* CAN */ #define GPIO_CAN1_RX GPIO_CAN1_RX_3 /* PD0 */ #define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */ -/* SPI - * SPI1 sensors 1 - * SPI2 FRAM + baro - * SPI5 sensors 2 - * SPI6 Reserved - * - */ + +/* SPI */ #define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */ #define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */ #define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */ @@ -313,19 +290,3 @@ /* I2C */ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */ #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */ - -#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -/* SDMMC1 - * - * VDD 3.3 - * GND - * SDMMC1_CK PC12 - * SDMMC1_CMD PD2 - * SDMMC1_D0 PC8 - * SDMMC1_D1 PC9 - * SDMMC1_D2 PC10 - * SDMMC1_D3 PC11 - */ - diff --git a/boards/mro/ctrl-zero-f7/nuttx-config/include/board_dma_map.h b/boards/mro/ctrl-zero-f7/nuttx-config/include/board_dma_map.h index 9191b174b9..c3df4fe607 100644 --- a/boards/mro/ctrl-zero-f7/nuttx-config/include/board_dma_map.h +++ b/boards/mro/ctrl-zero-f7/nuttx-config/include/board_dma_map.h @@ -74,7 +74,7 @@ | Channel 10 | SAI1_B | SAI2_B | SAI2_A | - | - | - | SAI1_A | - | | Channel 11 | SDMMC2 | - | QUADSPI | - | - | SDMMC2 | - | - | | | | | | | | | | | -| Usage | SPI1_RX_1 | | USART6_RX_2 | SPI1_TX_1 | SPI5_TX_1 | SPI5_RX_2 | SDMMC1_2 | USART6_TX_2 | +| Usage | SPI1_RX_1 | USART6_RX_2 | | SPI1_TX_1 | SPI5_TX_1 | SPI5_RX_2 | SDMMC1_2 | | */ // DMA1 Channel/Stream Selections @@ -89,10 +89,10 @@ // DMA2 Channel/Stream Selections //--------------------------------------------//---------------------------//---------------- #define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3 (SPI1 sensors RX) -// AVAILABLE // DMA2, Stream 1 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 // DMA2, Stream 2, Channel 5 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 // DMA2, Stream 1, Channel 5 +// AVAILABLE // DMA2, Stream 2 #define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI1 sensors TX) #define DMAMAP_SPI5_TX DMAMAP_SPI5_TX_1 // DMA2, Stream 4, Channel 3 (SPI5 sensors TX) #define DMAMAP_SPI5_RX DMAMAP_SPI5_RX_2 // DMA2, Stream 5, Channel 3 (SPI5 sensors RX) #define DMAMAP_SDMMC1 DMAMAP_SDMMC1_2 // DMA2, Stream 6, Channel 4 -#define DMAMAP_USART6_TX DMAMAP_USART6_TX_2 // DMA2, Stream 7, Channel 5 +// AVAILABLE // DMA2, Stream 7, Channel 5 diff --git a/boards/mro/ctrl-zero-f7/nuttx-config/scripts/script.ld b/boards/mro/ctrl-zero-f7/nuttx-config/scripts/script.ld index fc44eebedf..b68463a4d7 100644 --- a/boards/mro/ctrl-zero-f7/nuttx-config/scripts/script.ld +++ b/boards/mro/ctrl-zero-f7/nuttx-config/scripts/script.ld @@ -1,7 +1,7 @@ /**************************************************************************** * scripts/script.ld * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2019-2020 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * @@ -65,19 +65,19 @@ * where the code expects to begin execution by jumping to the entry point in * the 0x0800:0000 address range. * - * Bootloader reserves the first 32K bank (2 Mbytes Flash memory single bank) + * Bootloader reserves three 32K banks (2 Mbytes Flash memory single bank) * organization (256 bits read width) */ MEMORY { - FLASH_ITCM (rx) : ORIGIN = 0x00218000, LENGTH = 1952K - FLASH_AXIM (rx) : ORIGIN = 0x08018000, LENGTH = 1952K /* start on 4th sector (1st sector for bootloader, 2 for extra storage) */ + FLASH_ITCM (rx) : ORIGIN = 0x00218000, LENGTH = 1952K + FLASH_AXIM (rx) : ORIGIN = 0x08018000, LENGTH = 1952K /* start on 4th sector (1st sector for bootloader, 2 for extra storage) */ - ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 16K - DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K - SRAM1 (rwx) : ORIGIN = 0x20020000, LENGTH = 368K - SRAM2 (rwx) : ORIGIN = 0x2007c000, LENGTH = 16K + ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 16K + DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + SRAM1 (rwx) : ORIGIN = 0x20020000, LENGTH = 368K + SRAM2 (rwx) : ORIGIN = 0x2007c000, LENGTH = 16K } OUTPUT_ARCH(arm) diff --git a/boards/mro/ctrl-zero-f7/src/board_config.h b/boards/mro/ctrl-zero-f7/src/board_config.h index 58b7b289c5..671aa0b7ed 100644 --- a/boards/mro/ctrl-zero-f7/src/board_config.h +++ b/boards/mro/ctrl-zero-f7/src/board_config.h @@ -1,6 +1,6 @@ /**************************************************************************** * - * Copyright (c) 2019 PX4 Development Team. All rights reserved. + * Copyright (c) 2019-2020 PX4 Development Team. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -105,9 +105,7 @@ /* CAN Silence: Silent mode control \ ESC Mux select */ #define GPIO_CAN1_SILENT_S0 /* PF5 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTF|GPIO_PIN5) -/* PWM - * - */ +/* PWM */ #define DIRECT_PWM_OUTPUT_CHANNELS 8 #define DIRECT_INPUT_TIMER_CHANNELS 8 @@ -118,12 +116,10 @@ #define BOARD_NUMBER_BRICKS 1 #define GPIO_VDD_3V3_SPEKTRUM_POWER_EN /* PE4 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN4) -#define GPIO_VDD_3V3_SENSORS_EN /* PE3 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN3) - /* Define True logic Power Control in arch agnostic form */ -#define VDD_3V3_SPEKTRUM_POWER_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SPEKTRUM_POWER_EN, (on_true)) -#define READ_VDD_3V3_SPEKTRUM_POWER_EN() px4_arch_gpioread(GPIO_VDD_3V3_SPEKTRUM_POWER_EN) +#define VDD_3V3_SPEKTRUM_POWER_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SPEKTRUM_POWER_EN, (!on_true)) +#define READ_VDD_3V3_SPEKTRUM_POWER_EN() (px4_arch_gpioread(GPIO_VDD_3V3_SPEKTRUM_POWER_EN) == 0) /* Tone alarm output */ #define TONE_ALARM_TIMER 2 /* timer 2 */ @@ -134,22 +130,18 @@ #define GPIO_TONE_ALARM_IDLE GPIO_BUZZER_1 #define GPIO_TONE_ALARM GPIO_TIM2_CH1OUT_2 -/* USB OTG FS - * - * PA9 OTG_FS_VBUS VBUS sensing - */ +/* USB OTG FS */ #define GPIO_OTGFS_VBUS /* PA9 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN9) /* High-resolution timer */ #define HRT_TIMER 3 /* use timer3 for the HRT */ -#define HRT_TIMER_CHANNEL 3 /* use capture/compare channel 3 */ +#define HRT_TIMER_CHANNEL 2 /* use capture/compare channel 2 */ -#define HRT_PPM_CHANNEL /* T3C2 */ 2 /* use capture/compare channel 1 */ -#define GPIO_PPM_IN /* PC7 T3C2 */ GPIO_TIM3_CH2IN_3 +#define HRT_PPM_CHANNEL /* T3C3 */ 3 /* use capture/compare channel 3 */ +#define GPIO_PPM_IN /* PB0 T3C3 */ GPIO_TIM3_CH3IN_1 /* RC Serial port */ #define RC_SERIAL_PORT "/dev/ttyS3" -#define RC_SERIAL_SINGLEWIRE #define GPIO_RSSI_IN /* PC1 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN1) @@ -162,12 +154,11 @@ #define SPEKTRUM_POWER(_on_true) VDD_3V3_SPEKTRUM_POWER_EN(_on_true) /* - * FMUv5 has a separate RC_IN + * Board has a separate RC_IN * - * GPIO PPM_IN on PC7 T3CH2 - * SPEKTRUM_RX (it's TX or RX in Bind) on UART6 PG9 (NOT FMUv5 test HW ONLY) - * In version is possible in the UART - * and can drive GPIO PPM_IN as an output + * GPIO PPM_IN on PB0 T3CH3 + * SPEKTRUM_RX (it's TX or RX in Bind) on UART6 PC7 + * Inversion is possible in the UART and can drive GPIO_PPM_IN as an output */ #define GPIO_PPM_IN_AS_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN0) #define SPEKTRUM_RX_AS_GPIO_OUTPUT() px4_arch_configgpio(GPIO_PPM_IN_AS_OUT) @@ -201,7 +192,6 @@ GPIO_CAN1_SILENT_S0, \ GPIO_nPOWER_IN_A, \ GPIO_VDD_3V3_SPEKTRUM_POWER_EN, \ - GPIO_VDD_3V3_SENSORS_EN, \ GPIO_TONE_ALARM_IDLE, \ GPIO_SAFETY_SWITCH_IN, \ } diff --git a/boards/mro/ctrl-zero-f7/src/init.c b/boards/mro/ctrl-zero-f7/src/init.c index 0ca18a915f..cf89a1f3c3 100644 --- a/boards/mro/ctrl-zero-f7/src/init.c +++ b/boards/mro/ctrl-zero-f7/src/init.c @@ -1,6 +1,6 @@ /**************************************************************************** * - * Copyright (c) 2019 PX4 Development Team. All rights reserved. + * Copyright (c) 2019-2020 PX4 Development Team. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -100,9 +100,6 @@ __END_DECLS ************************************************************************************/ __EXPORT void board_peripheral_reset(int ms) { - /* set the peripheral rails off */ - board_control_spi_sensors_power(false, 0xffff); - bool last = READ_VDD_3V3_SPEKTRUM_POWER_EN(); /* Keep Spektum on to discharge rail*/ VDD_3V3_SPEKTRUM_POWER_EN(false); @@ -115,7 +112,6 @@ __EXPORT void board_peripheral_reset(int ms) /* switch the peripheral rail back on */ VDD_3V3_SPEKTRUM_POWER_EN(last); - board_control_spi_sensors_power(true, 0xffff); } /************************************************************************************ @@ -161,9 +157,7 @@ stm32_boardinitialize(void) /* configure pins */ const uint32_t gpio[] = PX4_GPIO_INIT_LIST; px4_gpio_init(gpio, arraySize(gpio)); - - /* configure SPI interfaces */ - px4_arch_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 0); + board_control_spi_sensors_power_configgpio(); /* configure USB interfaces */ stm32_usbinitialize(); @@ -198,7 +192,6 @@ stm32_boardinitialize(void) __EXPORT int board_app_initialize(uintptr_t arg) { /* Power on Interfaces */ - px4_arch_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 1); board_control_spi_sensors_power(true, 0xffff); VDD_3V3_SPEKTRUM_POWER_EN(true); diff --git a/boards/mro/ctrl-zero-f7/src/spi.cpp b/boards/mro/ctrl-zero-f7/src/spi.cpp index 99b912047f..c64c0d5a63 100644 --- a/boards/mro/ctrl-zero-f7/src/spi.cpp +++ b/boards/mro/ctrl-zero-f7/src/spi.cpp @@ -39,7 +39,7 @@ constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = { initSPIBus(SPI::Bus::SPI1, { initSPIDevice(DRV_IMU_DEVTYPE_ICM20602, SPI::CS{GPIO::PortC, GPIO::Pin2}, SPI::DRDY{GPIO::PortD, GPIO::Pin15}), initSPIDevice(DRV_IMU_DEVTYPE_ICM20948, SPI::CS{GPIO::PortE, GPIO::Pin15}, SPI::DRDY{GPIO::PortE, GPIO::Pin12}), - }), + }, {GPIO::PortE, GPIO::Pin3}), initSPIBus(SPI::Bus::SPI2, { initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortD, GPIO::Pin10}), initSPIDevice(DRV_BARO_DEVTYPE_DPS310, SPI::CS{GPIO::PortD, GPIO::Pin7}),