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@ -62,7 +62,7 @@
@@ -62,7 +62,7 @@
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#define rPCSEL(base) REG((base), STM32_ADC_PCSEL_OFFSET) |
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#define rCFG(base) REG((base), STM32_ADC_CFGR_OFFSET) |
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#define rCFG2(base) REG((base), STM32_ADC_CFGR2_OFFSET) |
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#define rCCR() REG((STM32_ADC1_BASE), (STM32_ADC_CCR_OFFSET)) |
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#define rCCR(base) REG((base), STM32_ADC_CCR_OFFSET) // Offset has ADC CMN included
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#define rSQR1(base) REG((base), STM32_ADC_SQR1_OFFSET) |
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#define rSQR2(base) REG((base), STM32_ADC_SQR2_OFFSET) |
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#define rSQR3(base) REG((base), STM32_ADC_SQR3_OFFSET) |
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@ -168,8 +168,8 @@ int px4_arch_adc_init(uint32_t base_address)
@@ -168,8 +168,8 @@ int px4_arch_adc_init(uint32_t base_address)
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/* enable the temperature sensor, VREFINT channel and VBAT */ |
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rCCR() = (ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN | |
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ADC_CCR_CKMODE_ASYCH | ADC_CCR_PRESC_DIV); |
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rCCR(base_address) = (ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN | |
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ADC_CCR_CKMODE_ASYCH | ADC_CCR_PRESC_DIV); |
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/* Enable ADC calibration. ADCALDIF == 0 so this is only for
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* single-ended conversions, not for differential ones. |
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