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stm32h7:ADC fix CCr Access

v1.13.0-BW
David Sidrane 3 years ago committed by Daniel Agar
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60231bbcb6
commit
1c224be8f6
1 changed files with 3 additions and 3 deletions
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  1. 4
      platforms/nuttx/src/px4/stm/stm32h7/adc/adc.cpp

4
platforms/nuttx/src/px4/stm/stm32h7/adc/adc.cpp
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@ -62,7 +62,7 @@
#define rPCSEL(base) REG((base), STM32_ADC_PCSEL_OFFSET) #define rPCSEL(base) REG((base), STM32_ADC_PCSEL_OFFSET)
#define rCFG(base) REG((base), STM32_ADC_CFGR_OFFSET) #define rCFG(base) REG((base), STM32_ADC_CFGR_OFFSET)
#define rCFG2(base) REG((base), STM32_ADC_CFGR2_OFFSET) #define rCFG2(base) REG((base), STM32_ADC_CFGR2_OFFSET)
#define rCCR() REG((STM32_ADC1_BASE), (STM32_ADC_CCR_OFFSET)) #define rCCR(base) REG((base), STM32_ADC_CCR_OFFSET) // Offset has ADC CMN included
#define rSQR1(base) REG((base), STM32_ADC_SQR1_OFFSET) #define rSQR1(base) REG((base), STM32_ADC_SQR1_OFFSET)
#define rSQR2(base) REG((base), STM32_ADC_SQR2_OFFSET) #define rSQR2(base) REG((base), STM32_ADC_SQR2_OFFSET)
#define rSQR3(base) REG((base), STM32_ADC_SQR3_OFFSET) #define rSQR3(base) REG((base), STM32_ADC_SQR3_OFFSET)
@ -168,7 +168,7 @@ int px4_arch_adc_init(uint32_t base_address)
/* enable the temperature sensor, VREFINT channel and VBAT */ /* enable the temperature sensor, VREFINT channel and VBAT */
rCCR() = (ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN | rCCR(base_address) = (ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN |
ADC_CCR_CKMODE_ASYCH | ADC_CCR_PRESC_DIV); ADC_CCR_CKMODE_ASYCH | ADC_CCR_PRESC_DIV);
/* Enable ADC calibration. ADCALDIF == 0 so this is only for /* Enable ADC calibration. ADCALDIF == 0 so this is only for

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