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@ -64,7 +64,7 @@
@@ -64,7 +64,7 @@
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/* Main PLL Configuration.
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* |
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* PLL source is HSE = 16,000,000 |
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* PLL source is HSE = 24,000,000 |
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* |
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* PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN |
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* Subject to: |
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@ -86,7 +86,7 @@
@@ -86,7 +86,7 @@
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/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
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* |
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* PLL1_VCO = (16,000,000 / 1) * 60 = 960 MHz |
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* PLL1_VCO = (24,000,000 / 2) * 80 = 960 MHz |
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* |
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* PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 480 MHz |
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* PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 240 MHz |
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