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Add support for STM32F100x value line. Contributed by Mike Smith. Still missing a file 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4955 7fd9a85b-ad96-42d3-883c-3090e2eb8679
sbg
patacongo 13 years ago
parent
0497992c2c
commit
43b043c496
8 changed files with 291 additions and 79 deletions
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  1. 8
      nuttx/ChangeLog
  2. 18
      nuttx/Documentation/NuttX.html
  3. 48
      nuttx/arch/arm/include/stm32/chip.h
  4. 69
      nuttx/arch/arm/include/stm32/stm32f10xxx_irq.h
  5. 4
      nuttx/arch/arm/src/stm32/chip.h
  6. 29
      nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
  7. 22
      nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
  8. 172
      nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c

8
nuttx/ChangeLog
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@ -3022,4 +3022,10 @@ @@ -3022,4 +3022,10 @@
* arch/arm/src/lpc43xx/lpc43_spifi.c, lpc43_spifi.h, and chip/lpc43_spifi.h:
Logic completely redesigned. It now creates an MTD driver to access SPIFI...
but the driver still does not work.
* arch/arm/src/stm32 and arch/arm/include/stm32: Make name of RTC ALARM interrupt
common on STM32 F1,2,4
* arch/arm/src/stm32 and arch/arm/include/stm32: Add add support for the
STM32F100x "Value Line" devices. This includes changes to stm32F10xx_rcc.c that
add the ability to run the chip off the internal oscillator. There is no open
board configuration for this part yet (the STM32F0Discovery or STM32VL boards
would be good candidates). Contributed by Mike Smith.

18
nuttx/Documentation/NuttX.html
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@ -8,7 +8,7 @@ @@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: July 12, 2012</p>
<p>Last Updated: July 19, 2012</p>
</td>
</tr>
</table>
@ -1097,7 +1097,7 @@ @@ -1097,7 +1097,7 @@
<li><a href="#arm7tdmi">ARM7TDMI</b></a> (5)</li>
<li><a href="#arm920t">ARM920T</a> (1) </li>
<li><a href="#arm926ejs">ARM926EJS</a> (3) </li>
<li><a href="#armcortexm3">ARM Cortex-M3</a> (15)</li>
<li><a href="#armcortexm3">ARM Cortex-M3</a> (16)</li>
<li><a href="#armcortexm4">ARM Cortex-M4</a> (5)</li>
</ul>
<li>Atmel AVR
@ -1620,6 +1620,20 @@ @@ -1620,6 +1620,20 @@
<td><br></td>
<td><hr></td>
</tr>
<tr>
<td><br></td>
<td>
<p>
<b>STMicro STM32F00x and STM32F107x</b>.
Chip support for these STM32 F1 families are present in NuttX and users have reported that they have successful brought up NuttX on there proprietary boards using this logic.
However, there is specific board support for these chip families.
</p>
</td>
</tr>
<tr>
<td><br></td>
<td><hr></td>
</tr>
<tr>
<td><br></td>
<td>

48
nuttx/arch/arm/include/stm32/chip.h
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@ -56,11 +56,43 @@ @@ -56,11 +56,43 @@
* the chip datasheet.
*/
#if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
#if defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
|| defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) \
|| defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* 16-bit general timers TIM2,3,4 with DMA */
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S (?) */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
@ -89,6 +121,7 @@ @@ -89,6 +121,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
@ -117,6 +150,7 @@ @@ -117,6 +150,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
@ -145,6 +179,7 @@ @@ -145,6 +179,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
@ -173,6 +208,7 @@ @@ -173,6 +208,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
@ -201,6 +237,7 @@ @@ -201,6 +237,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
@ -231,6 +268,7 @@ @@ -231,6 +268,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
@ -261,6 +299,7 @@ @@ -261,6 +299,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
@ -291,6 +330,7 @@ @@ -291,6 +330,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
@ -321,6 +361,7 @@ @@ -321,6 +361,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
@ -351,6 +392,7 @@ @@ -351,6 +392,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
@ -381,6 +423,7 @@ @@ -381,6 +423,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
@ -411,6 +454,7 @@ @@ -411,6 +454,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
@ -441,6 +485,7 @@ @@ -441,6 +485,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
@ -471,6 +516,7 @@ @@ -471,6 +516,7 @@
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */

69
nuttx/arch/arm/include/stm32/stm32f10xxx_irq.h
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@ -1,7 +1,7 @@ @@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/stm32s/stm32f10xxx_irq.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -61,7 +61,7 @@ @@ -61,7 +61,7 @@
* External interrupts (vectors >= 16)
*/
#ifdef CONFIG_STM32_CONNECTIVITY_LINE
#if defined(CONFIG_STM32_VALUELINE) && defined(CONFIG_STM32_MEDIUMDENSITY)
# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
@ -78,7 +78,70 @@ @@ -78,7 +78,70 @@
# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */
# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */
# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 7 global interrupt */
# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */
/* 19-22: reserved */
# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt (TIM16 global interrupt) */
# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts (TIM17 global interrupt) */
# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */
# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */
# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */
# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */
# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */
# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */
# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */
# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */
# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
# define STM32_IRQ_RTCALR (57) /* 41: RTC alarm through EXTI line interrupt */
# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */
# if defined(CONFIG_STM32_HIGHDENSITY)
# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */
# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */
# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */
/* 46-47: reserved */
# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
/* 49: reserved */
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
# define STM32_IRQ_SPI3 (67) /* 51: SPI1 global interrupt */
# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
# define STM32_IRQ_UART5 (69) /* 53: USART3 global interrupt */
# else
/* 43-53: reserved */
# endif
# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 global interrupt */
# define NR_IRQS (76)
#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */
# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */
# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */
# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */
# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */
# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */
# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */
# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */
# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */
# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */
# define STM32_IRQ_CAN1TX (35) /* 19: CAN1 TX interrupts */
# define STM32_IRQ_CAN1RX0 (36) /* 20: CAN1 RX0 interrupts */

4
nuttx/arch/arm/src/stm32/chip.h
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@ -49,7 +49,9 @@ @@ -49,7 +49,9 @@
/* Include the chip pin configuration file */
#if defined(CONFIG_STM32_STM32F10XX)
# if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
# if defined(CONFIG_STM32_VALUELINE)
# include "chip/stm32f100_pinmap.h"
# elif defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
# include "chip/stm32f103ze_pinmap.h"
# elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
# include "chip/stm32f103re_pinmap.h"

29
nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
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@ -52,6 +52,9 @@ @@ -52,6 +52,9 @@
#define STM32_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */
#define STM32_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */
#define STM32_RCC_CSR_OFFSET 0x0024 /* Control/status register */
#ifdef CONFIG_STM32_VALUELINE
# define STM32_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */
#endif
/* Register Addresses ***************************************************************/
@ -65,6 +68,9 @@ @@ -65,6 +68,9 @@
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
#ifdef CONFIG_STM32_VALUELINE
# define STM32_RCC_CFGR2 (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
@ -295,5 +301,28 @@ @@ -295,5 +301,28 @@
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */
#ifdef CONFIG_STM32_VALUELINE
/* Clock configuration register 2 */
# define RCC_CFGR2_PREDIV1d1 0 /* HSE input not divided */
# define RCC_CFGR2_PREDIV1d2 1 /* HSE input divided by 2 */
# define RCC_CFGR2_PREDIV1d3 2 /* HSE input divided by 3 */
# define RCC_CFGR2_PREDIV1d4 3 /* HSE input divided by 4 */
# define RCC_CFGR2_PREDIV1d5 4 /* HSE input divided by 5 */
# define RCC_CFGR2_PREDIV1d6 5 /* HSE input divided by 6 */
# define RCC_CFGR2_PREDIV1d7 6 /* HSE input divided by 7 */
# define RCC_CFGR2_PREDIV1d8 7 /* HSE input divided by 8 */
# define RCC_CFGR2_PREDIV1d9 8 /* HSE input divided by 9 */
# define RCC_CFGR2_PREDIV1d10 9 /* HSE input divided by 10 */
# define RCC_CFGR2_PREDIV1d11 10 /* HSE input divided by 11 */
# define RCC_CFGR2_PREDIV1d12 11 /* HSE input divided by 12 */
# define RCC_CFGR2_PREDIV1d13 12 /* HSE input divided by 13 */
# define RCC_CFGR2_PREDIV1d14 13 /* HSE input divided by 14 */
# define RCC_CFGR2_PREDIV1d15 14 /* HSE input divided by 15 */
# define RCC_CFGR2_PREDIV1d16 15 /* HSE input divided by 16 */
#endif
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RCC_H */

22
nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
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@ -43,7 +43,23 @@ @@ -43,7 +43,23 @@
* the interrupt vectors and handlers in their final form.
*/
#ifdef CONFIG_STM32_CONNECTIVITY_LINE
#if defined(CONFIG_STM32_VALUELINE)
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 60 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 60
#else
# error This target requires CONFIG_ARMV7M_CMNVECTOR
#endif /* CONFIG_ARMV7M_CMNVECTOR */
#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
@ -119,7 +135,7 @@ VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE inter @@ -119,7 +135,7 @@ VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE inter
VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */
#else /* CONFIG_STM32_CONNECTIVITY_LINE */
#else /* CONFIG_STM32_CONNECTIVITYLINE */
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
@ -195,4 +211,4 @@ VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3 @@ -195,4 +211,4 @@ VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3
VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45) /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */
#endif /* CONFIG_STM32_CONNECTIVITY_LINE */
#endif /* CONFIG_STM32_CONNECTIVITYLINE */

172
nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
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@ -415,92 +415,128 @@ static inline void rcc_enableapb2(void) @@ -415,92 +415,128 @@ static inline void rcc_enableapb2(void)
static inline void stm32_stdclockconfig(void)
{
uint32_t regval;
volatile int32_t timeout;
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
/* If the PLL is using the HSE, or the HSE is the system clock */
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
volatile int32_t timeout;
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
if (timeout == 0)
{
/* If so, then break-out with timeout > 0 */
/* In the case of a timeout starting the HSE, we really don't have a
* strategy. This is almost always a hardware failure or misconfiguration.
*/
break;
return;
}
}
/* Check for a timeout. If this timeout occurs, then we are hosed. We
* have no real back-up plan, although the following logic makes it look
* as though we do.
*/
/* If this is a value-line part and we are using the HSE as the PLL */
if (timeout > 0)
{
/* Enable FLASH prefetch buffer and 2 wait states */
# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
# endif
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the HSE prescaler */
/* Set the PCLK2 divider */
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
# endif
#endif
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PLL divider and multipler */
/* Value-line devices don't implement flash prefetch/waitstates */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
#ifndef CONFIG_STM32_VALUELINE
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
/* Enable FLASH prefetch buffer and 2 wait states */
/* Wait until the selected source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
}
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
/* If we are using the PLL, configure and start it */
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* Set the PLL divider and multipler */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
#endif
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the selected source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
}
#endif

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