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@ -713,36 +713,32 @@ LSM303D::check_extremes(const accel_report *arb)
@@ -713,36 +713,32 @@ LSM303D::check_extremes(const accel_report *arb)
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(int)arb->z_raw); |
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} |
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const uint8_t reglist[] = { ADDR_WHO_AM_I, ADDR_STATUS_A, ADDR_STATUS_M, ADDR_CTRL_REG0, ADDR_CTRL_REG1,
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ADDR_CTRL_REG2, ADDR_CTRL_REG3, ADDR_CTRL_REG4, ADDR_CTRL_REG5, ADDR_CTRL_REG6,
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ADDR_CTRL_REG7, ADDR_OUT_TEMP_L, ADDR_OUT_TEMP_H, ADDR_INT_CTRL_M, ADDR_INT_SRC_M,
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ADDR_REFERENCE_X, ADDR_REFERENCE_Y, ADDR_REFERENCE_Z, ADDR_OUT_X_L_A, ADDR_OUT_X_H_A,
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ADDR_OUT_Y_L_A, ADDR_OUT_Y_H_A, ADDR_OUT_Z_L_A, ADDR_OUT_Z_H_A, ADDR_FIFO_CTRL,
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ADDR_FIFO_SRC, ADDR_IG_CFG1, ADDR_IG_SRC1, ADDR_IG_THS1, ADDR_IG_DUR1, ADDR_IG_CFG2,
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ADDR_IG_SRC2, ADDR_IG_THS2, ADDR_IG_DUR2, ADDR_CLICK_CFG, ADDR_CLICK_SRC,
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ADDR_CLICK_THS, ADDR_TIME_LIMIT, ADDR_TIME_LATENCY, ADDR_TIME_WINDOW,
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ADDR_ACT_THS, ADDR_ACT_DUR, |
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ADDR_OUT_X_L_M, ADDR_OUT_X_H_M,
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ADDR_OUT_Y_L_M, ADDR_OUT_Y_H_M, ADDR_OUT_Z_L_M, ADDR_OUT_Z_H_M}; |
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uint8_t regval[sizeof(reglist)]; |
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for (uint8_t i=0; i<sizeof(reglist); i++) { |
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regval[i] = read_reg(reglist[i]); |
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} |
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// log registers at 10Hz when we have extreme values, or 0.5 Hz without
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if (_last_log_reg_us == 0 || |
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(is_extreme && (now - _last_log_reg_us > 500*1000)) || |
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(is_extreme && (now - _last_log_reg_us > 250*1000)) || |
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(now - _last_log_reg_us > 10*1000*1000)) { |
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_last_log_reg_us = now; |
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const uint8_t reglist[] = { ADDR_WHO_AM_I, ADDR_STATUS_A, ADDR_STATUS_M, ADDR_CTRL_REG0, ADDR_CTRL_REG1,
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ADDR_CTRL_REG2, ADDR_CTRL_REG3, ADDR_CTRL_REG4, ADDR_CTRL_REG5, ADDR_CTRL_REG6,
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ADDR_CTRL_REG7, ADDR_OUT_TEMP_L, ADDR_OUT_TEMP_H, ADDR_INT_CTRL_M, ADDR_INT_SRC_M,
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ADDR_REFERENCE_X, ADDR_REFERENCE_Y, ADDR_REFERENCE_Z, ADDR_OUT_X_L_A, ADDR_OUT_X_H_A,
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ADDR_OUT_Y_L_A, ADDR_OUT_Y_H_A, ADDR_OUT_Z_L_A, ADDR_OUT_Z_H_A, ADDR_FIFO_CTRL,
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ADDR_FIFO_SRC, ADDR_IG_CFG1, ADDR_IG_SRC1, ADDR_IG_THS1, ADDR_IG_DUR1, ADDR_IG_CFG2,
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ADDR_IG_SRC2, ADDR_IG_THS2, ADDR_IG_DUR2, ADDR_CLICK_CFG, ADDR_CLICK_SRC,
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ADDR_CLICK_THS, ADDR_TIME_LIMIT, ADDR_TIME_LATENCY, ADDR_TIME_WINDOW,
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ADDR_ACT_THS, ADDR_ACT_DUR, |
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ADDR_OUT_X_L_M, ADDR_OUT_X_H_M,
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ADDR_OUT_Y_L_M, ADDR_OUT_Y_H_M, ADDR_OUT_Z_L_M, ADDR_OUT_Z_H_M}; |
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::dprintf(_accel_log_fd, "FREG %llu", (unsigned long long)hrt_absolute_time()); |
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::dprintf(_accel_log_fd, "REG %llu", (unsigned long long)hrt_absolute_time()); |
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for (uint8_t i=0; i<sizeof(reglist); i++) { |
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::dprintf(_accel_log_fd, " %02x:%02x", (unsigned)reglist[i], (unsigned)read_reg(reglist[i])); |
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::dprintf(_accel_log_fd, " %02x:%02x", (unsigned)reglist[i], (unsigned)regval[i]); |
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} |
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::dprintf(_accel_log_fd, "\n"); |
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if (is_extreme) { |
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set_frequency(1000*1000); |
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::dprintf(_accel_log_fd, "SREG %llu", (unsigned long long)hrt_absolute_time()); |
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for (uint8_t i=0; i<sizeof(reglist); i++) { |
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::dprintf(_accel_log_fd, " %02x:%02x", (unsigned)reglist[i], (unsigned)read_reg(reglist[i])); |
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} |
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::dprintf(_accel_log_fd, "\n"); |
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set_frequency(8*1000*1000); |
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} |
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} |
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// fsync at 0.1Hz
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