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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4900 7fd9a85b-ad96-42d3-883c-3090e2eb8679sbg
patacongo
13 years ago
4 changed files with 1903 additions and 6 deletions
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/****************************************************************************************************
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* arch/arm/src/lpc43xx/chip/lpc43_lcd.h |
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* |
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* Copyright (C) 2012 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************************************/ |
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H |
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H |
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/****************************************************************************************************
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* Included Files |
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****************************************************************************************************/ |
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#include <nuttx/config.h> |
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/****************************************************************************************************
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* Pre-processor Definitions |
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****************************************************************************************************/ |
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/* Register Offsets *********************************************************************************/ |
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#define LPC43_LCD_TIMH_OFFSET 0x000 /* Horizontal Timing Control register */ |
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#define LPC43_LCD_TIMV_OFFSET 0x004 /* Vertical Timing Control register */ |
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#define LPC43_LCD_POL_OFFSET 0x008 /* Clock and Signal Polarity Control register */ |
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#define LPC43_LCD_LE_OFFSET 0x00c /* Line End Control register */ |
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#define LPC43_LCD_UPBASE_OFFSET 0x010 /* Upper Panel Frame Base Address register */ |
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#define LPC43_LCD_LPBASE_OFFSET 0x014 /* Lower Panel Frame Base Address register */ |
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#define LPC43_LCD_CTRL_OFFSET 0x018 /* LCD Control register */ |
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#define LPC43_LCD_INTMSK_OFFSET 0x01c /* Interrupt Mask register */ |
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#define LPC43_LCD_INTRAW_OFFSET 0x020 /* Raw Interrupt Status register */ |
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#define LPC43_LCD_INTSTAT_OFFSET 0x024 /* Masked Interrupt Status register */ |
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#define LPC43_LCD_INTCLR_OFFSET 0x028 /* Interrupt Clear register */ |
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#define LPC43_LCD_UPCURR_OFFSET 0x02c /* Upper Panel Current Address Value register */ |
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#define LPC43_LCD_LPCURR_OFFSET 0x030 /* Lower Panel Current Address Value register */ |
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/* 0x200 to 0x3fc 256x16-bit Color Palette registers */ |
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#define LPC43_LCD_PAL_OFFSET(n) (0x200 + ((n) << 2)) /* n=0..128, two colors per word */ |
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/* 0x800 to 0xbfc Cursor Image registers */ |
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#define LPC43_LCD_CRSR_IMG_OFFSET(n) (0x800 + ((n) << 2)) /* n = 0..256 */ |
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#define LPC43_LCD_CRSR_CTRL_OFFSET 0xc00 /* Cursor Control register */ |
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#define LPC43_LCD_CRSR_CFG_OFFSET 0xc04 /* Cursor Configuration register */ |
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#define LPC43_LCD_CRSR_PAL0_OFFSET 0xc08 /* Cursor Palette register 0 */ |
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#define LPC43_LCD_CRSR_PAL1_OFFSET 0xc0c /* Cursor Palette register 1 */ |
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#define LPC43_LCD_CRSR_XY_OFFSET 0xc10 /* Cursor XY Position register */ |
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#define LPC43_LCD_CRSR_CLIP_OFFSET 0xc14 /* Cursor Clip Position register */ |
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#define LPC43_LCD_CRSR_INTMSK_OFFSET 0xc20 /* Cursor Interrupt Mask register */ |
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#define LPC43_LCD_CRSR_INTCLR_OFFSET 0xc24 /* Cursor Interrupt Clear register */ |
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#define LPC43_LCD_CRSR_INTRAW_OFFSET 0xc28 /* Cursor Raw Interrupt Status register */ |
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#define LPC43_LCD_CRSR_INTSTAT_OFFSET 0xc2c /* Cursor Masked Interrupt Status register */ |
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/* Register Addresses *******************************************************************************/ |
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#define LPC43_LCD_TIMH (LPC43_LCD_BASE+LPC43_LCD_TIMH_OFFSET) |
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#define LPC43_LCD_TIMV (LPC43_LCD_BASE+LPC43_LCD_TIMV_OFFSET) |
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#define LPC43_LCD_POL (LPC43_LCD_BASE+LPC43_LCD_POL_OFFSET) |
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#define LPC43_LCD_LE (LPC43_LCD_BASE+LPC43_LCD_LE_OFFSET) |
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#define LPC43_LCD_UPBASE (LPC43_LCD_BASE+LPC43_LCD_UPBASE_OFFSET) |
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#define LPC43_LCD_LPBASE (LPC43_LCD_BASE+LPC43_LCD_LPBASE_OFFSET) |
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#define LPC43_LCD_CTRL (LPC43_LCD_BASE+LPC43_LCD_CTRL_OFFSET) |
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#define LPC43_LCD_INTMSK (LPC43_LCD_BASE+LPC43_LCD_INTMSK_OFFSET) |
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#define LPC43_LCD_INTRAW (LPC43_LCD_BASE+LPC43_LCD_INTRAW_OFFSET) |
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#define LPC43_LCD_INTSTAT (LPC43_LCD_BASE+LPC43_LCD_INTSTAT_OFFSET) |
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#define LPC43_LCD_INTCLR (LPC43_LCD_BASE+LPC43_LCD_INTCLR_OFFSET) |
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#define LPC43_LCD_UPCURR (LPC43_LCD_BASE+LPC43_LCD_UPCURR_OFFSET) |
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#define LPC43_LCD_LPCURR (LPC43_LCD_BASE+LPC43_LCD_LPCURR_OFFSET) |
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/* 0x200 to 0x3fc 256x16-bit Color Palette registers */ |
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#define LPC43_LCD_PAL(n) (LPC43_LCD_BASE+LPC43_LCD_PAL_OFFSET(n)) |
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/* 0x800 to 0xbfc Cursor Image registers */ |
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#define LPC43_LCD_CRSR_IMG(n) (LPC43_LCD_BASE+LPC43_LCD_CRSR_IMG_OFFSET(n)) |
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#define LPC43_LCD_CRSR_CTRL (LPC43_LCD_BASE+LPC43_LCD_CRSR_CTRL_OFFSET) |
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#define LPC43_LCD_CRSR_CFG (LPC43_LCD_BASE+LPC43_LCD_CRSR_CFG_OFFSET) |
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#define LPC43_LCD_CRSR_PAL0 (LPC43_LCD_BASE+LPC43_LCD_CRSR_PAL0_OFFSET) |
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#define LPC43_LCD_CRSR_PAL1 (LPC43_LCD_BASE+LPC43_LCD_CRSR_PAL1_OFFSET) |
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#define LPC43_LCD_CRSR_XY (LPC43_LCD_BASE+LPC43_LCD_CRSR_XY_OFFSET) |
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#define LPC43_LCD_CRSR_CLIP (LPC43_LCD_BASE+LPC43_LCD_CRSR_CLIP_OFFSET) |
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#define LPC43_LCD_CRSR_INTMSK (LPC43_LCD_BASE+LPC43_LCD_CRSR_INTMSK_OFFSET) |
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#define LPC43_LCD_CRSR_INTCLR (LPC43_LCD_BASE+LPC43_LCD_CRSR_INTCLR_OFFSET) |
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#define LPC43_LCD_CRSR_INTRAW (LPC43_LCD_BASE+LPC43_LCD_CRSR_INTRAW_OFFSET) |
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#define LPC43_LCD_CRSR_INTSTAT (LPC43_LCD_BASE+LPC43_LCD_CRSR_INTSTAT_OFFSET) |
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/* Register Bit Definitions *************************************************************************/ |
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/* Horizontal Timing Control register */ |
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/* Bits 0-1: Reserved */ |
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#define LCD_TIMH_PPL_SHIFT (2) /* Bits 2-7: Pixels-per-line */ |
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#define LCD_TIMH_PPL_MASK (0x3f << LCD_TIMH_PPL_SHIFT) |
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#define LCD_TIMH_HSW_SHIFT (8) /* Bits 8-15: Horizontal synchronization pulse width */ |
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#define LCD_TIMH_HSW_MASK (0xff << LCD_TIMH_HSW_SHIFT) |
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#define LCD_TIMH_HFP_SHIFT (16) /* Bits 16-23: Horizontal front porch */ |
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#define LCD_TIMH_HFP_MASK (0xff << LCD_TIMH_HFP_SHIFT) |
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#define LCD_TIMH_HBP_SHIFT (24) /* Bits 24-31: Horizontal back porch */ |
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#define LCD_TIMH_HBP_MASK (0xff << LCD_TIMH_HBP_SHIFT) |
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/* Bit nn: Reserved */ |
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/* Vertical Timing Control register */ |
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#define LCD_TIMV_LPP_SHIFT (0) /* Bits 0-9: Lines per panel */ |
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#define LCD_TIMV_LPP_MASK (0x3ff << LCD_TIMV_LPP_SHIFT) |
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#define LCD_TIMV_VSW_SHIFT (10) /* Bits 10-15: Vertical synchronization pulse width */ |
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#define LCD_TIMV_VSW_MASK (0x3f << LCD_TIMV_VSW_SHIFT) |
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#define LCD_TIMV_VFP_SHIFT (16) /* Bits 16-23: Vertical front porch */ |
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#define LCD_TIMV_VFP_MASK (0xff << LCD_TIMV_VFP_SHIFT) |
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#define LCD_TIMV_VBP_SHIFT (24) /* Bits 24-31: Vertical back porch */ |
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#define LCD_TIMV_VBP_MASK (0xff << LCD_TIMV_VBP_SHIFT) |
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/* Clock and Signal Polarity Control register */ |
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#define LCD_POL_PCDLO_SHIFT (0) /* Bits 0-4: Lower five bits of panel clock divisor */ |
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#define LCD_POL_PCDLO_MASK (31 << LCD_POL_PCDLO_SHIFT) |
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#define LCD_POL_CLKSEL (1 << 5) /* Bit 5: Clock Select */ |
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#define LCD_POL_ACB_SHIFT (6) /* Bits 6-10: AC bias pin frequency */ |
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#define LCD_POL_ACB_MASK (31 << LCD_POL_ACB_SHIFT) |
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#define LCD_POL_IVS (1 << 11) /* Bit 11: Invert vertical synchronization */ |
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#define LCD_POL_IHS (1 << 12) /* Bit 12: Invert horizontal synchronization */ |
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#define LCD_POL_IPC (1 << 13) /* Bit 13: Invert panel clock */ |
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#define LCD_POL_IOE (1 << 14) /* Bit 14: Invert output enable */ |
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/* Bit 15: Reserved */ |
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#define LCD_POL_CPL_SHIFT (16) /* Bits 16-25: Clocks per line */ |
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#define LCD_POL_CPL_MASK (0x3ff << LCD_POL_CPL_SHIFT) |
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#define LCD_POL_BCD (1 << 26) /* Bit 26: Bypass pixel clock divider */ |
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#define LCD_POL_PCDHI_SHIFT (27) /* Bits 27-31: Upper five bits of panel clock divisor */ |
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#define LCD_POL_PCDHI_MASK (31 << LCD_POL_PCDHI_SHIFT) |
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/* Line End Control register */ |
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#define LCD_LE_DELAY_SHIFT (0) /* Bits 0-6: Line-end delay */ |
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#define LCD_LE_DELAY_MASK (0x7f << LCD_LE_DELAY_SHIFT) |
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/* Bits 7-15: Reserved */ |
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#define LCD_LE_ENA (1 << 16) /* Bit 16: LCD Line end enable */ |
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/* Bits 17-31: Reserved */ |
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/* Upper Panel Frame Base Address register */ |
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/* Bits 0-2: Reserved */ |
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#define LCD_UPBASE_SHIFT (3) /* Bits 3-31: Upper panel base address */ |
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#define LCD_UPBASE_MASK (0xfffffff8) |
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/* Lower Panel Frame Base Address register */ |
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/* Bits 0-2: Reserved */ |
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#define LCD_LPBASE_SHIFT (3) /* Bits 3-31: Lower panel base address */ |
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#define LCD_LPBASE_MASK (0xfffffff8) |
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/* LCD Control register */ |
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#define LCD_CTRL_LCDEN (1 << 0) /* Bit 0: LCD enable control bit */ |
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#define LCD_CTRL_LCDBPP_SHIFT (1) /* Bits 1-3: LCD bits per pixel */ |
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#define LCD_CTRL_LCDBPP_MASK (7 << LCD_CTRL_LCDBPP_SHIFT) |
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# define LCD_CTRL_LCDBPP_1BPP (0 << LCD_CTRL_LCDBPP_SHIFT) /* 1 bpp */ |
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# define LCD_CTRL_LCDBPP_2BPP (1 << LCD_CTRL_LCDBPP_SHIFT) /* 2 bpp */ |
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# define LCD_CTRL_LCDBPP_4BPP (2 << LCD_CTRL_LCDBPP_SHIFT) /* 4 bpp */ |
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# define LCD_CTRL_LCDBPP_8BPP (3 << LCD_CTRL_LCDBPP_SHIFT) /* 8 bpp */ |
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# define LCD_CTRL_LCDBPP_16BPP (4 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp */ |
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# define LCD_CTRL_LCDBPP_24BPP (5 << LCD_CTRL_LCDBPP_SHIFT) /* 24 bpp (TFT panel only) */ |
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# define LCD_CTRL_LCDBPP_RGB565 (6 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp, 5:6:5 mode */ |
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# define LCD_CTRL_LCDBPP_RGB444 (7 << LCD_CTRL_LCDBPP_SHIFT) /* 12 bpp, 4:4:4 mode */ |
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#define LCD_CTRL_LCDBW (1 << 4) /* Bit 4: STN LCD monochrome/color selection */ |
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#define LCD_CTRL_LCDTFT (1 << 5) /* Bit 5: LCD panel TFT type selection */ |
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#define LCD_CTRL_LCDMONO8 (1 << 6) /* Bit 6: Monochrome LCD interface width */ |
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#define LCD_CTRL_LCDDUAL (1 << 7) /* Bit 7: Single or Dual LCD panel selection */ |
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#define LCD_CTRL_BGR (1 << 8) /* Bit 8: Color format selection */ |
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#define LCD_CTRL_BEBO (1 << 9) /* Bit 9: Big-endian Byte Order */ |
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#define LCD_CTRL_BEPO (1 << 10) /* Bit 10: Big-Endian Pixel Ordering */ |
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#define LCD_CTRL_LCDPWR (1 << 11) /* Bit 11: LCD power enable */ |
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#define LCD_CTRL_LCDVCOMP_SHIFT (12) /* Bits 12-13: LCD vertical compare interrupt */ |
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#define LCD_CTRL_LCDVCOMP_MASK (3 << LCD_CTRL_LCDVCOMP_SHIFT) |
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# define LCD_CTRL_LCDVCOMP_START (0 << LCD_CTRL_LCDVCOMP_SHIFT) /* Start of vertical synchronization */ |
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# define LCD_CTRL_LCDVCOMP_BACK (1 << LCD_CTRL_LCDVCOMP_SHIFT) /* Start of back porch */ |
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# define LCD_CTRL_LCDVCOMP_ACTIVE (2 << LCD_CTRL_LCDVCOMP_SHIFT) /* Start of active video */ |
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# define LCD_CTRL_LCDVCOMP_FRONT (3 << LCD_CTRL_LCDVCOMP_SHIFT) /* Start of front porch */ |
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/* Bits 14-15: Reserved */ |
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#define LCD_INTMSK_WATERMARK (1 << 16) /* Bit 16: LCD DMA FIFO watermark level */ |
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/* Bits 17-31: Reserved */ |
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/* Interrupt Mask register */ |
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/* Raw Interrupt Status register */ |
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/* Masked Interrupt Status register */ |
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/* Interrupt Clear register */ |
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/* Bit 0: Reserved */ |
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#define LCD_INT_FUFI (1 << 1) /* Bit 1: FIFO underflow interrupt */ |
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#define LCD_INT_LNBUI (1 << 2) /* Bit 2: LCD next base address update interrupt enable */ |
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#define LCD_INT_VCOMPI (1 << 3) /* Bit 3: Vertical compare interrupt enable */ |
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#define LCD_INT_BERI (1 << 4) /* Bit 4: AHB master error interrupt enable */ |
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/* Bits 5-31: Reserved */ |
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/* Upper Panel Current Address Value register (32-bit address) */ |
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/* Lower Panel Current Address Value register (32-bit address) */ |
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/* 256x16-bit Color Palette registers */ |
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#define LCD_PAL_R0_SHIFT (0) /* Bits 0-4: Red palette data */ |
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#define LCD_PAL_R0_MASK (31 << LCD_PAL_R0_SHIFT) |
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#define LCD_PAL_G0_SHIFT (5) /* Bits 5-9: Green palette data */ |
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#define LCD_PAL_G0_MASK (31 << LCD_PAL_G0_SHIFT) |
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#define LCD_PAL_B0_SHIFT (10) /* Bits 10-14: Blue palette data */ |
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#define LCD_PAL_B0_MASK (31 << LCD_PAL_B0_SHIFT) |
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#define LCD_PAL_I0 (1 << 16) /* Bit 15: Intensity / unused bit */ |
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#define LCD_PAL_R1_SHIFT (16) /* Bits 16-20: Red palette data */ |
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#define LCD_PAL_R1_MASK (31 << LCD_PAL_R1_SHIFT) |
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#define LCD_PAL_G1_SHIFT (21) /* Bits 21-25: Green palette data */ |
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#define LCD_PAL_G1_MASK (31 << LCD_PAL_G1_SHIFT) |
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#define LCD_PAL_B1_SHIFT (26) /* Bits 26-30: Blue palette data */ |
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#define LCD_PAL_B1_MASK (31 << LCD_PAL_B1_SHIFT) |
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#define LCD_PAL_I1 (1 << 31) /* Bit 31: Intensity / unused bit */ |
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/* Cursor Image registers (32-bit image data) */ |
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/* Cursor Control register */ |
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#define LCD_CRSR_CTRL_ON (1 << 0) /* Bit 0: Cursor enable */ |
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/* Bits 1-3: Reserved */ |
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#define LCD_CRSR_CTRL_NUM_SHIFT (4) /* Bits 4-5: Cursor image number */ |
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#define LCD_CRSR_CTRL_NUM_MASK (3 << LCD_CRSR_CTRL_NUM_SHIFT) |
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# define LCD_CRSR_CTRL_NUM_0 (0 << LCD_CRSR_CTRL_NUM_SHIFT) |
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# define LCD_CRSR_CTRL_NUM_1 (1 << LCD_CRSR_CTRL_NUM_SHIFT) |
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# define LCD_CRSR_CTRL_NUM_2 (2 << LCD_CRSR_CTRL_NUM_SHIFT) |
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# define LCD_CRSR_CTRL_NUM_3 (3 << LCD_CRSR_CTRL_NUM_SHIFT) |
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/* Bits 6-31: Reserved */ |
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/* Cursor Configuration register */ |
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#define LCD_CRSR_CFG_CRSRSIZE (1 << 0) /* Bit 0: Cursor size selection */ |
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#define LCD_CRSR_CFG_FRAMESYNC (1 << 1) /* Bit 1: Cursor frame synchronization type */ |
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/* Bits 2-31: Reserved */ |
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/* Cursor Palette register 0/1 */ |
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#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color component */ |
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#define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL_RED_SHIFT) |
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#define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ |
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#define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL_GREEN_SHIFT) |
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#define LCD_CRSR_PAL_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */ |
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#define LCD_CRSR_PAL_BLUE_MASK (0xff << LCD_CRSR_PAL_BLUE_SHIFT) |
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/* Bits 24-31: Reserved */ |
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/* Cursor XY Position register */ |
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#define LCD_CRSRX_SHIFT (0) /* Bits 0-9: X ordinate of the cursor origin measured in pixels */ |
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#define LCD_CRSRX_MASK (0x3ff << LCD_CRSRX_SHIFT) |
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/* Bits 10-15: Reserved */ |
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#define LCD_CRSRY_SHIFT (16) /* Bits 16-25: Y ordinate of the cursor origin measured in pixels */ |
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#define LCD_CRSRY_MASK (0x3ff << LCD_CRSRY_SHIFT) |
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/* Bits 26-31: Reserved */ |
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/* Cursor Clip Position register */ |
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#define LCD_CRSR_CLIPX_SHIFT (0) /* Bits 0-5: Cursor clip position for X direction */ |
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#define LCD_CRSR_CLIPX_MASK (0x3f << LCD_CRSR_CLIPX_SHIFT) |
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/* Bits 6-7: Reserved */ |
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#define LCD_CRSR_CLIPY_SHIFT (8) /* Bits 8-13: Cursor clip position for Y direction */ |
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#define LCD_CRSR_CLIPY_MASK (0x3f << LCD_CRSR_CLIPY_SHIFT) |
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/* Bits 14-31: Reserved */ |
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/* Cursor Interrupt Mask register */ |
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/* Cursor Interrupt Clear register */ |
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/* Cursor Raw Interrupt Status register */ |
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/* Cursor Masked Interrupt Status register */ |
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#define LCD_CRSR_INT (1 << 0) /* CRSRIM Cursor interrupt */ |
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/* Bits 1-31: Reserved */ |
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/****************************************************************************************************
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* Public Types |
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****************************************************************************************************/ |
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/****************************************************************************************************
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* Public Data |
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****************************************************************************************************/ |
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/****************************************************************************************************
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* Public Functions |
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****************************************************************************************************/ |
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H */ |
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