diff --git a/boards/px4/fmu-v5x/nuttx-config/include/board.h b/boards/px4/fmu-v5x/nuttx-config/include/board.h index 1cdc8ce1f8..c0eaf85117 100644 --- a/boards/px4/fmu-v5x/nuttx-config/include/board.h +++ b/boards/px4/fmu-v5x/nuttx-config/include/board.h @@ -38,6 +38,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ +#include "board_dma_map.h" #include @@ -242,20 +243,6 @@ # define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif -/* DMA Channel/Stream Selections *****************************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * if we set aside more DMA channels/streams. - * - * SDMMC RX and TX DMA is on DMA2 - * - * SDMMC2 DMA - * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 - * DMAMAP_SDMMC2_2 = Channel 11, Stream 5 <- Free for other devices - */ - -#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 - - /* FLASH wait states * * --------- ---------- ----------- @@ -355,17 +342,6 @@ * GPIO_UART8_TX PE1 */ -/* U[x]ART DMA configurations */ - -// #define DMAMAP_UART5_RX - DMA1, STREAM 0, Chan 4 - not remapable -// #define DMAMAP_UART5_TX - DMA1, STREAM 7, Chan 4 - not remapable - -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 /* DMA2, STREAM 1, Chan 5 */ -#define DMAMAP_USART6_TX DMAMAP_USART6_TX_2 /* DMA2, STREAM 7, Chan 5 */ - -// #define DMAMAP_UART7_RX - DMA1, STREAM 3, Chan 5 - not remapable - -// #define DMAMAP_UART8_RX - DMA1, STREAM 6, Chan 5 - not remapable /* CAN * diff --git a/boards/px4/fmu-v5x/nuttx-config/include/board_dma_map.h b/boards/px4/fmu-v5x/nuttx-config/include/board_dma_map.h new file mode 100644 index 0000000000..bc9578bb53 --- /dev/null +++ b/boards/px4/fmu-v5x/nuttx-config/include/board_dma_map.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * + * Copyright (c) 2020 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#pragma once + + +// DMA1 Channel/Stream Selections +//--------------------------------------------//---------------------------//---------------- +// DMAMAP_UART5_RX // DMA1, Stream 0, Channel 4 (TELEM2 RX) +#define DMAMAP_SPI2_RX DMAMAP_SPI2_RX_1 // DMA1, Stream 1, Channel 9 (SPI2 RX) +#define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_2 // DMA1, Stream 2, Channel 0 (SPI3 RX) +// DMAMAP_UART7_RX // DMA1, Stream 3, Channel 5 (TELEM1 RX) +#define DMAMAP_SPI2_TX DMAMAP_SPI2_TX_2 // DMA1, Stream 4, Channel 0 (SPI2 TX) +#define DMAMAP_SPI3_TX DMAMAP_SPI3_TX_1 // DMA1, Stream 5, Channel 0 (SPI3 TX) +// DMAMAP_TIM4_UP // DMA1, Stream 6, Channel 2 (DSHOT) + +// DMA2 Channel/Stream Selections +//--------------------------------------------//---------------------------//---------------- +#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 // DMA2, Stream 0, Channel 11 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 // DMA2, Stream 1, Channel 5 (PX4IO) +#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3 (SPI sensors RX) +#define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI sensors TX) +// AVAILABLE // DMA2, Stream 4 +// DMAMAP_TIM1_UP // DMA2, Stream 5, Channel 6 (DSHOT) +// AVAILABLE // DMA2, Stream 6 +#define DMAMAP_USART6_TX DMAMAP_USART6_TX_2 // DMA2, Stream 7, Channel 5 (PX4IO) diff --git a/boards/px4/fmu-v5x/nuttx-config/nsh/defconfig b/boards/px4/fmu-v5x/nuttx-config/nsh/defconfig index d7e719b739..6c3dee8750 100644 --- a/boards/px4/fmu-v5x/nuttx-config/nsh/defconfig +++ b/boards/px4/fmu-v5x/nuttx-config/nsh/defconfig @@ -220,10 +220,14 @@ CONFIG_STM32F7_SDMMC_DMA=y CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y CONFIG_STM32F7_SPI1=y +CONFIG_STM32F7_SPI1_DMA=y CONFIG_STM32F7_SPI2=y +CONFIG_STM32F7_SPI2_DMA=y CONFIG_STM32F7_SPI3=y +CONFIG_STM32F7_SPI3_DMA=y CONFIG_STM32F7_SPI5=y CONFIG_STM32F7_SPI6=y +CONFIG_STM32F7_SPI_DMA=y CONFIG_STM32F7_TIM10=y CONFIG_STM32F7_TIM11=y CONFIG_STM32F7_TIM3=y diff --git a/boards/px4/fmu-v5x/src/board_config.h b/boards/px4/fmu-v5x/src/board_config.h index 9192f65643..43d57b6df8 100644 --- a/boards/px4/fmu-v5x/src/board_config.h +++ b/boards/px4/fmu-v5x/src/board_config.h @@ -543,7 +543,7 @@ /* This board provides a DMA pool and APIs */ -#define BOARD_DMA_ALLOC_POOL_SIZE 5120+4096 +#define BOARD_DMA_ALLOC_POOL_SIZE (5120 + 4096 + 1024 + 1024) // 5120 fat + 4096 + 1024 + 1024 spi /* This board provides the board_on_reset interface */