STM32 CAN driver now compiles

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4210 7fd9a85b-ad96-42d3-883c-3090e2eb8679

nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h

@@ -122,19 +122,19 @@
 
 /* CAN */
 
-#define GPIO_CAN1_RX_1        (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN11)
-#define GPIO_CAN1_RX_2        (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_CAN1_RX_3        (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN0)
-#define GPIO_CAN1_RX_4        (GPIO_ALT|GPIO_AF9|GPIO_PORTI|GPIO_PIN9)
-#define GPIO_CAN1_TX_1        (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN12)
-#define GPIO_CAN1_TX_2        (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN9)
-#define GPIO_CAN1_TX_3        (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN1)
-#define GPIO_CAN1_TX_4        (GPIO_ALT|GPIO_AF9|GPIO_PORTH|GPIO_PIN13)
-
-#define GPIO_CAN2_RX_1        (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_CAN2_RX_2        (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN5)
-#define GPIO_CAN2_TX_1        (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_CAN2_TX_2        (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_CAN1_RX_1        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_CAN1_RX_2        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_CAN1_RX_3        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
+#define GPIO_CAN1_RX_4        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
+#define GPIO_CAN1_TX_1        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_CAN1_TX_2        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_CAN1_TX_3        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1)
+#define GPIO_CAN1_TX_4        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
+
+#define GPIO_CAN2_RX_1        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_CAN2_RX_2        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_CAN2_TX_1        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_CAN2_TX_2        (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
 
 /* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
  * (PA4 or PA5) is automatically connected to the analog converter output

nuttx/arch/arm/src/stm32/stm32_pwm.c

@@ -815,10 +815,10 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_
 static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 {
   FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
-
   uint32_t resetbit;
   uint32_t regaddr;
   uint32_t regval;
+  irqstate_t flags;
 
   pwmvdbg("TIM%d\n", priv->timid);
 
@@ -898,6 +898,12 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 #endif
     }
 
+  /* Disable interrupts momentary to stop any ongoing timer processing and
+   * to prevent any concurrent access to the reset register.
+  */
+
+  flags = irqsave();
+
   /* Reset the timer - stopping the output and putting the timer back
    * into a state where pwm_start() can be called.
    */
@@ -908,6 +914,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 
   regval &= ~resetbit;
   putreg32(regval, regaddr);
+  irqrestore(flags);
 
   pwmvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
   pwm_dumpregs(priv, "After stop");

nuttx/configs/stm3240g-eval/README.txt

@@ -15,6 +15,7 @@ Contents
   - LEDs
   - Ethernet
   - PWM
+  - CAN
   - Configurations
 
 Development Environment
@@ -220,6 +221,40 @@ FSMC must be disabled in this case!  PD13 is available at:
   TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD.
   Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14.
 
+CAN
+===
+
+Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2.
+
+  JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver
+  JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver
+
+CAN signals are then available on CN10 pins:
+
+  CN10 Pin 7 = CANH
+  CN10 Pin 2 = CANL
+
+Mapping to STM32 GPIO pins:
+
+  PD0   = FSMC_D2 & CAN1_RX   
+  PD1   = FSMC_D3 & CAN1_TX   
+  PB13  = ULPI_D6 & CAN2_TX
+  PB5   = ULPI_D7 & CAN2_RX
+
+Configuration Options:
+
+  CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+    CONFIG_STM32_CAN2 must also be defined)
+  CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+    Default: 8
+  CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+    Default: 4
+
+  CONFIG_STM32_CAN1 - Enable support for CAN1
+  CONFIG_CAN1_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN1 is defined.
+  CONFIG_STM32_CAN2 - Enable support for CAN1
+  CONFIG_CAN2_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN2 is defined.
+
 STM3240G-EVAL-specific Configuration Options
 ============================================
 

nuttx/configs/stm3240g-eval/include/board.h

@@ -301,6 +301,32 @@
 
 #define GPIO_TIM4_CH2 GPIO_TIM4_CH2_2
 
+/* CAN
+ *
+ * Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2.
+ *
+ *   JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver
+ *   JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver
+ *
+ * CAN signals are then available on CN10 pins:
+ *
+ *   CN10 Pin 7 = CANH
+ *   CN10 Pin 2 = CANL
+ *
+ * Mapping to STM32 GPIO pins:
+ *
+ *   PD0   = FSMC_D2 & CAN1_RX   
+ *   PD1   = FSMC_D3 & CAN1_TX   
+ *   PB13  = ULPI_D6 & CAN2_TX
+ *   PB5   = ULPI_D7 & CAN2_RX
+ */
+
+#define GPIO_CAN1_RX        GPIO_CAN1_RX_3
+#define GPIO_CAN1_TX        GPIO_CAN1_TX_3
+
+#define GPIO_CAN2_RX        GPIO_CAN2_RX_2
+#define GPIO_CAN2_TX        GPIO_CAN2_TX_1
+
 /************************************************************************************
  * Public Data
  ************************************************************************************/

nuttx/include/nuttx/can.h

@@ -89,11 +89,14 @@
 /* CAN message support */
 
 #define CAN_MAXDATALEN 8
+
 #define CAN_ID(hdr)               ((uint16_t)(hdr) >> 5)
 #define CAN_RTR(hdr)              (((hdr) & 0x0010) != 0)
 #define CAN_DLC(hdr)              ((hdr) & 0x0f)
 #define CAN_MSGLEN(hdr)           (sizeof(struct can_msg_s) - (CAN_MAXDATALEN - CAN_DLC(hdr)))
 
+#define CAN_MSG(id, rtr, dlc)     ((uint16_t)id << 5 | (uint16_t)rtr << 4 | (uint16_t)dlc)
+
 /* Built-in ioctl commands
  *
  * CANIOCTL_RTR: Send the remote transmission request and wait for the response.