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boards: STM32H7 pad to 256 bit - 32 bytes (#19724)

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David Sidrane 3 years ago committed by GitHub
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1ba3610cfc
commit
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GPG Key ID: 4AEE18F83AFDEB23
17 changed files with 271 additions and 202 deletions
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  1. 8
      boards/cuav/nora/nuttx-config/scripts/script.ld
  2. 8
      boards/cuav/x7pro/nuttx-config/scripts/script.ld
  3. 7
      boards/cubepilot/cubeorange/nuttx-config/scripts/script.ld
  4. 40
      boards/holybro/durandal-v1/nuttx-config/scripts/script.ld
  5. 40
      boards/holybro/kakuteh7/nuttx-config/scripts/script.ld
  6. 48
      boards/matek/h743-mini/nuttx-config/scripts/script.ld
  7. 46
      boards/matek/h743-slim/nuttx-config/scripts/script.ld
  8. 46
      boards/matek/h743/nuttx-config/scripts/script.ld
  9. 40
      boards/modalai/fc-v2/nuttx-config/scripts/script.ld
  10. 18
      boards/mro/ctrl-zero-classic/nuttx-config/scripts/script.ld
  11. 18
      boards/mro/ctrl-zero-h7-oem/nuttx-config/scripts/script.ld
  12. 18
      boards/mro/ctrl-zero-h7/nuttx-config/scripts/script.ld
  13. 8
      boards/mro/pixracerpro/nuttx-config/scripts/script.ld
  14. 40
      boards/px4/fmu-v6c/nuttx-config/scripts/script.ld
  15. 41
      boards/px4/fmu-v6u/nuttx-config/scripts/script.ld
  16. 40
      boards/px4/fmu-v6x/nuttx-config/scripts/script.ld
  17. 7
      boards/spracing/h7extreme/nuttx-config/scripts/script.ld

8
boards/cuav/nora/nuttx-config/scripts/script.ld
Unescape View File

@ -111,6 +111,7 @@ MEMORY @@ -111,6 +111,7 @@ MEMORY
{
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
@ -186,7 +187,12 @@ SECTIONS @@ -186,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > AXI_SRAM AT > FLASH
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);

8
boards/cuav/x7pro/nuttx-config/scripts/script.ld
Unescape View File

@ -111,6 +111,7 @@ MEMORY @@ -111,6 +111,7 @@ MEMORY
{
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
@ -186,7 +187,12 @@ SECTIONS @@ -186,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > AXI_SRAM AT > FLASH
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);

7
boards/cubepilot/cubeorange/nuttx-config/scripts/script.ld
Unescape View File

@ -187,7 +187,12 @@ SECTIONS @@ -187,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > AXI_SRAM AT > FLASH
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);

40
boards/holybro/durandal-v1/nuttx-config/scripts/script.ld
Unescape View File

@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -156,7 +157,7 @@ SECTIONS @@ -156,7 +157,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -165,17 +166,17 @@ SECTIONS @@ -165,17 +166,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -186,7 +187,12 @@ SECTIONS @@ -186,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -195,7 +201,7 @@ SECTIONS @@ -195,7 +201,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -204,7 +210,7 @@ SECTIONS @@ -204,7 +210,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

40
boards/holybro/kakuteh7/nuttx-config/scripts/script.ld
Unescape View File

@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1792K /* params in last sector */
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1792K /* params in last sector */
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -156,7 +157,7 @@ SECTIONS @@ -156,7 +157,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -165,17 +166,17 @@ SECTIONS @@ -165,17 +166,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -186,7 +187,12 @@ SECTIONS @@ -186,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -195,7 +201,7 @@ SECTIONS @@ -195,7 +201,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -204,7 +210,7 @@ SECTIONS @@ -204,7 +210,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

48
boards/matek/h743-mini/nuttx-config/scripts/script.ld
Unescape View File

@ -1,7 +1,7 @@ @@ -1,7 +1,7 @@
/****************************************************************************
* scripts/script.ld
*
* Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
* Copyright (C) 2020 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
*
@ -34,7 +34,7 @@ @@ -34,7 +34,7 @@
*
****************************************************************************/
/* The Durandal-v1 uses an STM32H743II has 2048Kb of main FLASH memory.
/* The board uses an STM32H743II and has 2048Kb of main FLASH memory.
* The flash memory is partitioned into a User Flash memory and a System
* Flash memory. Each of these memories has two banks:
*
@ -59,8 +59,8 @@ @@ -59,8 +59,8 @@
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x1FF0:0000
*
* The Durandal has a Swtich on board, the BOOT0 pin is at ground so by default,
* the STM32 will boot to address 0x0800:0000 in FLASH unless the swiutch is
* There's a switch on board, the BOOT0 pin is at ground so by default,
* the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is
* drepresed, then the boot will be from 0x1FF0:0000
*
* The STM32H743ZI also has 1024Kb of data SRAM.
@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -156,7 +157,7 @@ SECTIONS @@ -156,7 +157,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -165,17 +166,17 @@ SECTIONS @@ -165,17 +166,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -186,7 +187,12 @@ SECTIONS @@ -186,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -195,7 +201,7 @@ SECTIONS @@ -195,7 +201,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -204,7 +210,7 @@ SECTIONS @@ -204,7 +210,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

46
boards/matek/h743-slim/nuttx-config/scripts/script.ld
Unescape View File

@ -34,7 +34,7 @@ @@ -34,7 +34,7 @@
*
****************************************************************************/
/* The Durandal-v1 uses an STM32H743II has 2048Kb of main FLASH memory.
/* The board uses an STM32H743II and has 2048Kb of main FLASH memory.
* The flash memory is partitioned into a User Flash memory and a System
* Flash memory. Each of these memories has two banks:
*
@ -59,8 +59,8 @@ @@ -59,8 +59,8 @@
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x1FF0:0000
*
* The Durandal has a Swtich on board, the BOOT0 pin is at ground so by default,
* the STM32 will boot to address 0x0800:0000 in FLASH unless the swiutch is
* There's a switch on board, the BOOT0 pin is at ground so by default,
* the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is
* drepresed, then the boot will be from 0x1FF0:0000
*
* The STM32H743ZI also has 1024Kb of data SRAM.
@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -156,7 +157,7 @@ SECTIONS @@ -156,7 +157,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -165,17 +166,17 @@ SECTIONS @@ -165,17 +166,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -186,7 +187,12 @@ SECTIONS @@ -186,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -195,7 +201,7 @@ SECTIONS @@ -195,7 +201,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -204,7 +210,7 @@ SECTIONS @@ -204,7 +210,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

46
boards/matek/h743/nuttx-config/scripts/script.ld
Unescape View File

@ -34,7 +34,7 @@ @@ -34,7 +34,7 @@
*
****************************************************************************/
/* The Durandal-v1 uses an STM32H743II has 2048Kb of main FLASH memory.
/* The board uses an STM32H743II and has 2048Kb of main FLASH memory.
* The flash memory is partitioned into a User Flash memory and a System
* Flash memory. Each of these memories has two banks:
*
@ -59,8 +59,8 @@ @@ -59,8 +59,8 @@
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x1FF0:0000
*
* The Durandal has a Swtich on board, the BOOT0 pin is at ground so by default,
* the STM32 will boot to address 0x0800:0000 in FLASH unless the swiutch is
* There's a switch on board, the BOOT0 pin is at ground so by default,
* the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is
* drepresed, then the boot will be from 0x1FF0:0000
*
* The STM32H743ZI also has 1024Kb of data SRAM.
@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -156,7 +157,7 @@ SECTIONS @@ -156,7 +157,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -165,17 +166,17 @@ SECTIONS @@ -165,17 +166,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -186,7 +187,12 @@ SECTIONS @@ -186,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -195,7 +201,7 @@ SECTIONS @@ -195,7 +201,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -204,7 +210,7 @@ SECTIONS @@ -204,7 +210,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

40
boards/modalai/fc-v2/nuttx-config/scripts/script.ld
Unescape View File

@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -157,7 +158,7 @@ SECTIONS @@ -157,7 +158,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -166,17 +167,17 @@ SECTIONS @@ -166,17 +167,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -187,7 +188,12 @@ SECTIONS @@ -187,7 +188,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -196,7 +202,7 @@ SECTIONS @@ -196,7 +202,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -205,7 +211,7 @@ SECTIONS @@ -205,7 +211,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

18
boards/mro/ctrl-zero-classic/nuttx-config/scripts/script.ld
Unescape View File

@ -187,7 +187,12 @@ SECTIONS @@ -187,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > AXI_SRAM AT > FLASH
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -199,6 +204,7 @@ SECTIONS @@ -199,6 +204,7 @@ SECTIONS
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
.sram4_reserve (NOLOAD) :
{
*(.sram4)
@ -206,7 +212,6 @@ SECTIONS @@ -206,7 +212,6 @@ SECTIONS
_sram4_heap_start = ABSOLUTE(.);
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
@ -220,13 +225,4 @@ SECTIONS @@ -220,13 +225,4 @@ SECTIONS
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.ramfunc : {
_sramfuncs = .;
*(.ramfunc .ramfunc.*)
. = ALIGN(4);
_eramfuncs = .;
} > ITCM_RAM AT > FLASH
_framfuncs = LOADADDR(.ramfunc);
}

18
boards/mro/ctrl-zero-h7-oem/nuttx-config/scripts/script.ld
Unescape View File

@ -187,7 +187,12 @@ SECTIONS @@ -187,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > AXI_SRAM AT > FLASH
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -199,6 +204,7 @@ SECTIONS @@ -199,6 +204,7 @@ SECTIONS
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
.sram4_reserve (NOLOAD) :
{
*(.sram4)
@ -206,7 +212,6 @@ SECTIONS @@ -206,7 +212,6 @@ SECTIONS
_sram4_heap_start = ABSOLUTE(.);
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
@ -220,13 +225,4 @@ SECTIONS @@ -220,13 +225,4 @@ SECTIONS
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.ramfunc : {
_sramfuncs = .;
*(.ramfunc .ramfunc.*)
. = ALIGN(4);
_eramfuncs = .;
} > ITCM_RAM AT > FLASH
_framfuncs = LOADADDR(.ramfunc);
}

18
boards/mro/ctrl-zero-h7/nuttx-config/scripts/script.ld
Unescape View File

@ -187,7 +187,12 @@ SECTIONS @@ -187,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > AXI_SRAM AT > FLASH
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -199,6 +204,7 @@ SECTIONS @@ -199,6 +204,7 @@ SECTIONS
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
.sram4_reserve (NOLOAD) :
{
*(.sram4)
@ -206,7 +212,6 @@ SECTIONS @@ -206,7 +212,6 @@ SECTIONS
_sram4_heap_start = ABSOLUTE(.);
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
@ -220,13 +225,4 @@ SECTIONS @@ -220,13 +225,4 @@ SECTIONS
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.ramfunc : {
_sramfuncs = .;
*(.ramfunc .ramfunc.*)
. = ALIGN(4);
_eramfuncs = .;
} > ITCM_RAM AT > FLASH
_framfuncs = LOADADDR(.ramfunc);
}

8
boards/mro/pixracerpro/nuttx-config/scripts/script.ld
Unescape View File

@ -111,6 +111,7 @@ MEMORY @@ -111,6 +111,7 @@ MEMORY
{
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
@ -186,7 +187,12 @@ SECTIONS @@ -186,7 +187,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > AXI_SRAM AT > FLASH
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);

40
boards/px4/fmu-v6c/nuttx-config/scripts/script.ld
Unescape View File

@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -157,7 +158,7 @@ SECTIONS @@ -157,7 +158,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -166,17 +167,17 @@ SECTIONS @@ -166,17 +167,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -187,7 +188,12 @@ SECTIONS @@ -187,7 +188,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -196,7 +202,7 @@ SECTIONS @@ -196,7 +202,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -205,7 +211,7 @@ SECTIONS @@ -205,7 +211,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

41
boards/px4/fmu-v6u/nuttx-config/scripts/script.ld
Unescape View File

@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -157,7 +158,7 @@ SECTIONS @@ -157,7 +158,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -166,17 +167,17 @@ SECTIONS @@ -166,17 +167,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -187,7 +188,12 @@ SECTIONS @@ -187,7 +188,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -196,7 +202,7 @@ SECTIONS @@ -196,7 +202,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -205,8 +211,7 @@ SECTIONS @@ -205,8 +211,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

40
boards/px4/fmu-v6x/nuttx-config/scripts/script.ld
Unescape View File

@ -109,16 +109,17 @@ @@ -109,16 +109,17 @@
MEMORY
{
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
flash (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
AXI_SRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K /* D1 domain AXI bus */
SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K /* D2 domain AHB bus */
SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K /* D2 domain AHB bus */
SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K /* D2 domain AHB bus */
SRAM4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K /* D3 domain */
BKPRAM (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
}
OUTPUT_ARCH(arm)
@ -157,7 +158,7 @@ SECTIONS @@ -157,7 +158,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > FLASH
/*
* Init functions (static constructors and the like)
@ -166,17 +167,17 @@ SECTIONS @@ -166,17 +167,17 @@ SECTIONS
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
} > FLASH
.ARM.extab : {
*(.ARM.extab*)
} > flash
} > FLASH
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -187,7 +188,12 @@ SECTIONS @@ -187,7 +188,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > AXI_SRAM AT > FLASH = 0xffff
.bss : {
_sbss = ABSOLUTE(.);
@ -196,7 +202,7 @@ SECTIONS @@ -196,7 +202,7 @@ SECTIONS
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
@ -205,7 +211,7 @@ SECTIONS @@ -205,7 +211,7 @@ SECTIONS
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
} > SRAM4
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }

7
boards/spracing/h7extreme/nuttx-config/scripts/script.ld
Unescape View File

@ -239,7 +239,12 @@ SECTIONS @@ -239,7 +239,12 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > qspi
/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
. = ALIGN(16);
FILL(0xffff)
. += 16;
} > sram AT > qspi = 0xffff
.bss : {
_sbss = ABSOLUTE(.);

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