David Sidrane
|
bfc704b60a
|
fmuk66-v3:Add pullup on LPUART0_RX
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6 years ago |
Daniel Agar
|
744bacd424
|
boards/ enforce astyle
|
6 years ago |
|
David Sidrane
|
729d1c32d3
|
Rename nxphlite-v3 to NXP fmuk66-v3 (#10927)
|
6 years ago |
|
Daniel Agar
|
3e0a3559a9
|
cmake use standard mechanisms for settings flags
|
6 years ago |
|
Daniel Agar
|
f692ad04d0
|
boards organization
|
6 years ago |
|
David Sidrane
|
f0663fb143
|
nxphlite-v3:Match probes to V3 HW
|
7 years ago |
|
Daniel Agar
|
02c4ec9b2a
|
move nuttx-configs to platforms/nuttx
|
7 years ago |
|
David Sidrane
|
812128d565
|
nxphlite-v3:V3.5 HW changes
|
8 years ago |
|
David Sidrane
|
df2b5e420f
|
nxphlite-v3:Define PWM and Capture
|
8 years ago |
|
David Sidrane
|
6e2885cc4e
|
nxphlite-v3:Board mods to support 1 Mhz FTM
|
8 years ago |
|
David Sidrane
|
2f2f1ff8ea
|
nxphlite-v3:Use 8bit io on usart access for inversion
Fix comment
Use 8bit io on usart access for inversion, 32 bit
on odd address was causwing BUS access hard fault.
|
8 years ago |
|
David Sidrane
|
ebaf8479c5
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nxphlite-v3:Clock configuration for TPM
|
8 years ago |
|
David Sidrane
|
8fd5fb00a3
|
nxphlite-v1:Add Debug probes
|
8 years ago |
|
David Sidrane
|
5aa449f226
|
nxphlite-v3:Set FRDIV to 512 to keep clock in spec
|
8 years ago |
|
David Sidrane
|
9a0fbe5623
|
Inital commit of nxphlite-v3 per v3 schematic
|
8 years ago |
|
David Sidrane
|
7cde985e27
|
WIP nxphlite-v3
Configure Clocking, USB and Console on LPUART
|
8 years ago |
|
David Sidrane
|
d409ca3e46
|
Inital commit of nxphlite-v3
|
8 years ago |
|
David Sidrane
|
0e23df28ea
|
Removed STM32 references from Kinetis
|
8 years ago |
|
David Sidrane
|
23e45cb4b3
|
nxphlite-v1 Refreshed nuttx SDIO changes for 7.19+
|
8 years ago |
|
David Sidrane
|
c1812af45e
|
Inital commit of NXPhlite-v1
|
8 years ago |
