- new IMU driver structure with state machine (no sleeps in bus thread)
- verify all configured registers and trigger reset on failure
- detect if DIO1 or DIO2 are actually connected for data ready interrupt usage
- don't use CRC-16 on burst transfers except for verified lots
- currently the main change is that it reduces the max number of ORB multi instances to 4, but usage will be expanded as needed
- limits number of EKF2 multi instances to 2.
- enabled on all cortex m4 boards
- generate PWM_MAIN 1-14
- generate PWM_AUX 1-8
- generate PWM_EXTRA 1-8
- px4io and pwm_out directly read configuration parameters
- only available and active physical outputs are actually shown for configuration
- overall saves flash despite adding many new parameters
- increase stack sizes to run cleanly under stackcheck
- this is likely overkill for most boards, but using stackcheck to set our minimum ensures we have a very safe margin on regular builds and it's something we can currently afford
- remove holybro_durandal-v1_stackcheck from test rack (there's only one unit)
- interupt pin set active low and latch
- relax retry timeout if configure failed
- improve configured empty rate (sample rate) rounding
- fix RegisterCheck
- check FIFO count as part of full transfer and reset or adjust timing if necessary
- rename DRV_IMU_DEVTYPE_ICM20608 -> DRV_IMU_DEVTYPE_ICM20608G
- update to NuttX with stm32f4 and stm32f7 SPI DMA internal buffers
- remove explicit DMA buffer allocations from new IMU drivers
- restore original BOARD_DMA_ALLOC_POOL_SIZE
- decrease SPI DMA thresholds based on fmu-v2/v3/v4/v5 bench testing
Julian Oes
Daniel Agar
David Sidrane
Matthias Grob
Beat Küng
flbernier
SalimTerryLi
mcsauder