Tree: c09e9ec97f

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my1.12

my1.12-iic

pr-sensor-distance

release/1.12

sbg

tf-1.12

tf-1.12-print_test

tf-iic2uart

tf_driver-1.12

tf_i2c-1.12

tf_i2c_collis_pre

v1.13.0-BW

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Commit Graph

7 Commits (c09e9ec97f96cfefdcacbfb7f77310be56397456)

Author	SHA1	Message	Date
David Sidrane	1c212e3f84	M7 dcache ctrl via a parameter (#11769) ... * Support for armv7-m_dcache control via parameter The FORCE_F7_DCACHE parameter can be set to 0 - (default) if Eratta exits turn dcache off else leave it on 1 - Force it off 2 - Force it on At boot the system will disable the d-cache if the silicon has the 1259864 Data corruption in a sequence of Write-Through stores and loads eratta. Post nsh script execution the FORCE_F7_DCACHE paramater will be used to set the d-cache to the state indicated above.	6 years ago
Daniel Agar	f6cd70bcc5	px4_fmu-v5 nsh compress defconfig	6 years ago
David Sidrane	edd9f91a19	board:Set larger stack margin	6 years ago
David Sidrane	b40f8d52a8	STM32F7 disable d-cache as a precaution (#11374) ... - see 1259864 Data corruption in a sequence of Write-Through stores and loads - if we can be certain this sequence won't occur in PX4 then the d-cache will be re-enabled	6 years ago
David Sidrane	0f5f4814bb	px4_fmu-v5: Inital commit NuttX 7.27+	6 years ago
Daniel Agar	abb3817d31	boards new split VENDOR_MODEL naming convention	6 years ago
Daniel Agar	f692ad04d0	boards organization	6 years ago