So that clang 12 does not complain:
loop variable 'child' is always a copy because the range of type 'List<ModuleParams *>' does not return a reference
Co-authored-by: Yashom Dighe <yashom7@gmail.com>
120 seconds of learning time in 3D fusion mode was too long for most normal flights. The learned bias is usually really good after a shorter period and was not used to update the parameters. 30s seems to be a good compromise.
So that clang 12 does not complain:
loop variable 'child' is always a copy because the range of type 'List<ModuleParams *>' does not return a reference
- this relative path was incorrect for the px4io when using the Makefile generator and built for inclusion within another build (eg px4_fmu-v5_default)
- simplifies creation of an airframe config
- could be done from QGC, but it only knows if a param is non-default from
metadata, which can be incorrect/missing information
- for the list of exceptions we could look at '@category', but we don't have
that info in the build
- there might be some more exceptions to be added
* Add jsbsim bridge to enable jsbsim for px4 SITL/HIL on jsbsim
This is a PX4 HIL/SITL integration into JSBSim. JSBSim is an open source flight dynamics model (http://jsbsim.sourceforge.net/)
Currently there are three models available which is the rascal, quadrotor_x, hexarotor_x integrated into the bridge.
The simulation can be run with the firmware with the following command for example
```
make px4_sitl jsbsim_rascal
```
The visualization is done flightgear and is done by the bridge sending UDP packets to flightgear. To disable the visualization `HEADLESS=1` when running the make command.
The simulation can be configured through the configuration files under the `config` directory through a xml file. Senor configurations, The xml file name should match the name of the model.
* Update Tools/sitl_run.sh
Co-authored-by: Beat Küng <beat-kueng@gmx.net>
Co-authored-by: Beat Küng <beat-kueng@gmx.net>
Daniel Agar
Yashom Dighe
bresch
Beat Küng
bazooka joe
jaeyoung
David Sidrane