This is a back port of upstream NuttX PX4 contrib of
ef42c25 stm32f7:SDMMC add dcache alignment check in dma{recv|send}setup
In the where CONFIG_SDIO_PREFLIGHT is not used and dcache
write-buffed mode is used (not write-through) buffer alignment
is required for DMA transfers because a) arch_invalidate_dcache
could lose buffered writes data and b) arch_flush_dcache could
corrupt adjacent memory if the buffer and the bufflen, are not on
ARMV7M_DCACHE_LINESIZE boundaries.
1e7ddfe stm32f7:SDMMC remove widebus limitation on DMA
There is no documantation for the STM32F7 that limits DMA on
1 bit vrs 4 bit mode.
dffab2f stm32f7:DMA add dcache alignment check in stm32_dmacapable
In the case dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data and
b) arch_flush_dcache could corrupt adjacent memory if the
maddr and the mend+1, the next next address are not on
ARMV7M_DCACHE_LINESIZE boundaries.
38cbf1f stm32f7:DMA correct comments and document stm32_dmacapable
Updated comment to proper refernce manual for STM32F7 not STM32F4.
Added stm32_dmacapable input paramaters documentation.
David Sidrane