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/************************************************************************************ |
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* configs/px4fmu-v4pro/include/board.h |
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* include/arch/board/board.h |
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* |
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* Copyright (C) 2009, 2016 Gregory Nutt. All rights reserved. |
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* Authors: Gregory Nutt <gnutt@nuttx.org> |
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* David Sidrane <david_s5@nscdg.com> |
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* Kevin Lopez Alvarez <kevin@drotek.com> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#ifndef __NUTTX_CONFIG_PX4FMUV4_PRO_INCLUDE_BOARD_H |
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#define __NUTTX_CONFIG_PX4FMUV4_PRO_INCLUDE_BOARD_H |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include <stm32.h> |
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/************************************************************************************ |
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* Definitions |
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************************************************************************************/ |
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/* Clocking *************************************************************************/ |
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/* The PX4FMUV4-PRO uses a 24MHz crystal connected to the HSE. |
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* |
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* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c: |
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* System Clock source : PLL (HSE) |
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* SYSCLK(Hz) : 180000000 Determined by PLL configuration |
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* HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) |
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) |
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) |
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) |
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* HSE Frequency(Hz) : 24000000 (STM32_BOARD_XTAL) |
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* PLLM : 12 (STM32_PLLCFG_PLLM) |
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* PLLN : 180 (STM32_PLLCFG_PLLN) |
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* PLLP : 2 (STM32_PLLCFG_PLLP) |
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* PLLQ : 2 (STM32_PLLCFG_PPQ) |
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK |
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* Flash Latency(WS) : 5 |
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* Prefetch Buffer : OFF |
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* Instruction cache : ON |
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* Data cache : ON |
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* Require 48MHz for USB OTG FS, : Use PLLSA1M |
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* SDIO and RNG clock |
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*/ |
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/* HSI - 16 MHz RC factory-trimmed |
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* LSI - 32 KHz RC |
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* HSE - On-board crystal frequency is 24MHz |
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* LSE - not installed |
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*/ |
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#define STM32_BOARD_XTAL 24000000ul |
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#define STM32_HSI_FREQUENCY 16000000ul |
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#define STM32_LSI_FREQUENCY 32000 |
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL |
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/* Main PLL Configuration. |
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* |
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* PLL source is HSE |
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN |
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* = (24,000,000 / 12) * 180 |
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* = 369,000,000 |
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* SYSCLK = PLL_VCO / PLLP |
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* = 360,000,000 / 2 = 180,000,000 |
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* USB OTG FS, SDIO and RNG Clock is from PLL SAIP |
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* = 48,000,000 |
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*/ |
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(12) |
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(180) |
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 |
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(2) |
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) |
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/* Configure factors for PLLSAI clock */ |
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(96) |
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(4) |
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) |
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) |
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/* Configure Dedicated Clock Configuration Register */ |
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#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1) |
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#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1) |
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#define STM32_RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_DIV2 |
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#define STM32_RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_PLLSAI |
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#define STM32_RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_PLLI2S |
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#define STM32_RCC_DCKCFGR_TIMPRE 0 |
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#define STM32_RCC_DCKCFGR_48MSEL RCC_DCKCFGR_48MSEL_PLLSAI |
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#define STM32_RCC_DCKCFGR_SDMMCSEL RCC_DCKCFGR_SDMMCSEL_48MHZ |
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#define STM32_RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_DSIPHY |
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/* Configure factors for PLLI2S clock */ |
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(96) |
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(4) |
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) |
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#define STM32_SYSCLK_FREQUENCY 180000000ul |
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/* AHB clock (HCLK) is SYSCLK (180MHz) */ |
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ |
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY |
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ |
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/* APB1 clock (PCLK1) is HCLK/4 (45MHz) */ |
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ |
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) |
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/* Timers driven from APB1 will be twice PCLK1 */ |
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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/* APB2 clock (PCLK2) is HCLK/2 (90MHz) */ |
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ |
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* Timers driven from APB2 will be twice PCLK2 */ |
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx |
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* otherwise frequency is 2xAPBx. |
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* Note: TIM1,8-11 are on APB2, others on APB1 |
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*/ |
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#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN |
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#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN |
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#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN |
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#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN |
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#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN |
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#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN |
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#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN |
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#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN |
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#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN |
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#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN |
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#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN |
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#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN |
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#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN |
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#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN |
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/* SDMMC dividers. Note that slower clocking is required when DMA is disabled |
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* in order to avoid RX overrun/TX underrun errors due to delayed responses |
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* to service FIFOs in interrupt driven mode. These values have not been |
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* tuned!!! |
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* |
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* SDIOCLK =48MHz, SDMMC_CK=SDIOCLK/(118+2)=400 KHz |
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*/ |
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/* Use the Falling edge of the SDIO_CLK clock to change the edge the |
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* data and commands are change on |
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*/ |
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#define SDIO_CLKCR_EDGE SDIO_CLKCR_NEGEDGE |
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#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) |
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/* DMA ON: SDIOCLK=48MHz, SDMMC_CK=SDIOCLK/(1+2)=16 MHz |
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* DMA OFF: SDIOCLK=48MHz, SDMMC_CK=SDIOCLK/(2+2)=12 MHz |
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*/ |
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#ifdef CONFIG_STM32_SDIO_DMA |
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# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* DMA ON: SDIOCLK=48MHz, SDMMC_CK=SDIOCLK/(1+2)=16 MHz |
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* DMA OFF: SDIOCLK=48MHz, SDMMC_CK=SDIOCLK/(2+2)=12 MHz |
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*/ |
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//TODO #warning "Check Freq for 24mHz" |
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#ifdef CONFIG_STM32_SDIO_DMA |
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* DMA Channel/Stream Selections *****************************************************/ |
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/* Stream selections are arbitrary for now but might become important in the future |
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* is we set aside more DMA channels/streams. |
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* |
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* SDIO DMA |
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* DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA |
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* DMAMAP_SDIO_2 = Channel 4, Stream 6 |
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*/ |
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#define DMAMAP_SDIO DMAMAP_SDIO_1 |
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/* FLASH wait states |
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* |
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* --------- ---------- ----------- --------- |
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* VDD MAX SYSCLK WAIT STATES OVERDRIVE |
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* --------- ---------- ----------- --------- |
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* 1.7-2.1 V 168 MHz 8 OFF |
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* 2.1-2.4 V 180 MHz 8 ON |
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* 2.4-2.7 V 180 MHz 7 ON |
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* 2.7-3.6 V 180 MHz 5 ON |
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* --------- ---------- ----------- -------- |
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*- |
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*/ |
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#define BOARD_FLASH_WAITSTATES 5 |
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/* LED definitions ******************************************************************/ |
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/* The px4fmu-v4pro board has numerous LEDs. |
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* FMU_LED_RED, FMU_LED_GREEN & FMU_LED_BLUE are directly connected and |
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* can be controlled by software. |
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* |
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way. |
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* The following definitions are used to access individual LEDs. |
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*/ |
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/* LED index values for use with board_userled() */ |
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#define BOARD_LED1 0 |
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#define BOARD_LED2 1 |
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#define BOARD_LED3 2 |
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#define BOARD_NLEDS 3 |
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#define BOARD_LED_RED BOARD_LED1 |
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#define BOARD_LED_GREEN BOARD_LED2 |
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#define BOARD_LED_BLUE BOARD_LED3 |
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/* LED bits for use with board_userled_all() */ |
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#define BOARD_LED1_BIT (1 << BOARD_LED1) |
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#define BOARD_LED2_BIT (1 << BOARD_LED2) |
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#define BOARD_LED3_BIT (1 << BOARD_LED3) |
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in |
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* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related |
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* events as follows: |
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* |
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* |
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* SYMBOL Meaning LED state |
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* Red Green Blue |
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* ---------------------- -------------------------- ------ ------ ----*/ |
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ |
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ |
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ |
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ |
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ |
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ |
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ |
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ |
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ |
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/* Thus if the Green LED is statically on, NuttX has successfully booted and |
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* is, apparently, running normally. If the Red LED is flashing at |
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* approximately 2Hz, then a fatal error has been detected and the system |
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* has halted. |
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*/ |
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/* Alternate function pin selections ************************************************/ |
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/* |
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* UARTs. |
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*/ |
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#define GPIO_USART1_RX GPIO_USART1_RX_2 /* ESP8266 */ |
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#define GPIO_USART1_TX GPIO_USART1_TX_2 |
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#define GPIO_USART2_RX GPIO_USART2_RX_2 |
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#define GPIO_USART2_TX GPIO_USART2_TX_2 |
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2 |
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#define GPIO_USART2_CTS GPIO_USART2_CTS_2 |
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#define GPIO_USART3_RX GPIO_USART3_RX_3 |
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#define GPIO_USART3_TX GPIO_USART3_TX_3 |
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#define GPIO_USART3_RTS GPIO_USART3_RTS_2 |
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#define GPIO_USART3_CTS GPIO_USART3_CTS_2 |
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#define GPIO_UART4_RX GPIO_UART4_RX_1 |
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#define GPIO_UART4_TX GPIO_UART4_TX_1 |
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* RC_INPUT */ |
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#define GPIO_USART6_TX GPIO_USART6_TX_1 |
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#define GPIO_UART7_RX GPIO_UART7_RX_1 |
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#define GPIO_UART7_TX GPIO_UART7_TX_1 |
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/* UART8 has no alternate pin config */ |
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/* UART RX DMA configurations */ |
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#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 |
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 |
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/* |
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* CAN |
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* |
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* CAN1 is routed to the onboard transceiver. |
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*/ |
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3 |
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3 |
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#define GPIO_CAN2_RX GPIO_CAN2_RX_1 |
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#define GPIO_CAN2_TX GPIO_CAN2_TX_1 |
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/* |
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* I2C |
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* |
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* The optional _GPIO configurations allow the I2C driver to manually |
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* reset the bus to clear stuck slaves. They match the pin configuration, |
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* but are normally-high GPIOs. |
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*/ |
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 |
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 |
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#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) |
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#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) |
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 |
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 |
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#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTF|GPIO_PIN1) |
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#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTF|GPIO_PIN0) |
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/* |
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* SPI |
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* |
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* There are sensors on SPI1, and SPI2 is connected to the FRAM. |
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*/ |
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 |
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 |
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 |
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 |
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 |
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_1 |
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#define GPIO_SPI5_MISO GPIO_SPI5_MISO_1 |
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#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_1 |
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#define GPIO_SPI5_SCK GPIO_SPI5_SCK_1 |
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#define GPIO_SPI5_NSS GPIO_SPI5_NSS_1 |
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/* Board provides GPIO or other Hardware for signaling to timing analyzer */ |
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#if defined(CONFIG_BOARD_USE_PROBES) |
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# define PROBE_N(n) (1<<((n)-1)) |
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# define PROBE_1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14) |
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# define PROBE_2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN13) |
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# define PROBE_3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11) |
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# define PROBE_4 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9) |
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# define PROBE_5 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN13) |
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# define PROBE_6 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN14) |
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# define PROBE_INIT(mask) \ |
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do { \ |
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if ((mask)& PROBE_N(1)) { stm32_configgpio(PROBE_1); } \ |
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if ((mask)& PROBE_N(2)) { stm32_configgpio(PROBE_2); } \ |
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if ((mask)& PROBE_N(3)) { stm32_configgpio(PROBE_3); } \ |
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if ((mask)& PROBE_N(4)) { stm32_configgpio(PROBE_4); } \ |
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if ((mask)& PROBE_N(5)) { stm32_configgpio(PROBE_5); } \ |
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if ((mask)& PROBE_N(6)) { stm32_configgpio(PROBE_6); } \ |
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} while(0) |
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# define PROBE(n,s) do {stm32_gpiowrite(PROBE_##n,(s));}while(0) |
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# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true) |
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#else |
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# define PROBE_INIT(mask) |
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# define PROBE(n,s) |
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# define PROBE_MARK(n) |
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#endif |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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#undef EXTERN |
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#if defined(__cplusplus) |
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#define EXTERN extern "C" |
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extern "C" { |
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#else |
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#define EXTERN extern |
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#endif |
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/************************************************************************************ |
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* Public Function Prototypes |
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************************************************************************************/ |
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/************************************************************************************ |
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* Name: stm32_boardinitialize |
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* |
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* Description: |
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* All STM32 architectures must provide the following entry point. This entry point |
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* is called early in the initialization -- after all memory has been configured |
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* and mapped but before any devices have been initialized. |
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* |
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************************************************************************************/ |
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EXTERN void stm32_boardinitialize(void); |
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#undef EXTERN |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __NUTTX_CONFIG_PX4FMUV4_PRO_INCLUDE_BOARD_H */
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