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121 lines
5.1 KiB
121 lines
5.1 KiB
/************************************************************************************ |
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* configs/olimex-stm32-p107/include/board.h |
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* |
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* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include "stm32_rcc.h" |
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#include "stm32_sdio.h" |
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#include "stm32_internal.h" |
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/************************************************************************************ |
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* Pre-processor Definitions |
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************************************************************************************/ |
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/* Clocking *************************************************************************/ |
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/* On-board crystal frequency is 25MHz (HSE) */ |
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#define STM32_BOARD_XTAL 25000000ul |
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/* PLL ouput is 72MHz */ |
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#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ |
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#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ |
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#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ |
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#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ |
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#define STM32_PLL_FREQUENCY (72000000) |
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/* SYCLLK and HCLK are the PLL frequency */ |
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY |
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY |
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ |
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/* APB2 clock (PCLK2) is HCLK (72MHz) */ |
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK |
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY |
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ |
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/* APB2 timers 1 and 8 will receive PCLK2. */ |
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) |
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ |
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 |
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */ |
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) |
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/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as: |
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* |
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* STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz |
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*/ |
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#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) |
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# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ |
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# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ |
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#endif |
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/************************************************************************************ |
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* Public Function Prototypes |
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************************************************************************************/ |
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/************************************************************************************ |
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* Name: stm32_boardinitialize |
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* |
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* Description: |
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* All STM32 architectures must provide the following entry point. This entry point |
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* is called early in the intitialization -- after all memory has been configured |
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* and mapped but before any devices have been initialized. |
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* |
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************************************************************************************/ |
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void stm32_boardinitialize(void);
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