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/************************************************************************************ |
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* nuttx-configs/omnibus-f4sd/include/board.h |
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* include/arch/board/board.h |
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* |
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* Copyright (C) 2012 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Copyright (c) 2018 PX4 Development Team. All rights reserved. |
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* Author: Nathan Tsoi <nathan@vertile.com> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#ifndef __CONFIG_OMNIBUSF4SD_INCLUDE_BOARD_H |
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#define __CONFIG_OMNIBUSF4SD_INCLUDE_BOARD_H |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include "stm32_rcc.h" |
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#include "stm32_sdio.h" |
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#include "stm32.h" |
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/************************************************************************************ |
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* Definitions |
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************************************************************************************/ |
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/* Clocking *************************************************************************/ |
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/* The omnibusf4sd board features a single 8MHz crystal. Space is provided |
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* for a 32kHz RTC backup crystal, but it is not stuffed. |
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* |
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* This is the canonical configuration: |
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* System Clock source : PLL (HSE) |
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration |
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) |
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) |
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) |
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) |
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* HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) |
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* PLLM : 8 (STM32_PLLCFG_PLLM) |
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* PLLN : 336 (STM32_PLLCFG_PLLN) |
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* PLLP : 2 (STM32_PLLCFG_PLLP) |
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* PLLQ : 7 (STM32_PLLCFG_PLLQ) |
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK |
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* Flash Latency(WS) : 5 |
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* Prefetch Buffer : OFF |
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* Instruction cache : ON |
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* Data cache : ON |
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* Require 48MHz for USB OTG FS, : Enabled |
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* SDIO and RNG clock |
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*/ |
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/* HSI - 16 MHz RC factory-trimmed |
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* LSI - 32 KHz RC |
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* HSE - On-board crystal frequency is 8MHz |
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* LSE - 32.768 kHz |
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*/ |
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#define STM32_BOARD_XTAL 8000000ul |
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#define STM32_HSI_FREQUENCY 16000000ul |
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#define STM32_LSI_FREQUENCY 32000 |
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL |
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#define STM32_LSE_FREQUENCY 32768 |
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/* Main PLL Configuration. |
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* |
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* PLL source is HSE |
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN |
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* = (8,000,000 / 8) * 336 |
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* = 336,000,000 |
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* SYSCLK = PLL_VCO / PLLP |
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* = 336,000,000 / 2 = 168,000,000 |
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* USB OTG FS, SDIO and RNG Clock |
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* = PLL_VCO / PLLQ |
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* = 48,000,000 |
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*/ |
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) |
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) |
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 |
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) |
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#define STM32_SYSCLK_FREQUENCY 168000000ul |
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/* AHB clock (HCLK) is SYSCLK (168MHz) */ |
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ |
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY |
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ |
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ |
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ |
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) |
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/* Timers driven from APB1 will be twice PCLK1 */ |
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ |
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ |
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* Timers driven from APB2 will be twice PCLK2 */ |
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx |
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* otherwise frequency is 2xAPBx. |
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* Note: TIM1,8-11 are on APB2, others on APB1 |
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*/ |
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#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN |
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#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN |
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#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN |
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#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN |
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#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN |
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#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN |
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#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN |
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#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN |
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#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN |
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#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN |
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#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN |
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#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN |
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#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN |
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#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN |
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled |
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* in order to avoid RX overrun/TX underrun errors due to delayed responses |
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* to service FIFOs in interrupt driven mode. These values have not been |
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* tuned!!! |
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* |
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz |
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*/ |
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#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) |
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz |
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz |
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*/ |
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#ifdef CONFIG_STM32_SDIO_DMA |
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# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz |
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz |
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*/ |
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#ifdef CONFIG_STM32_SDIO_DMA |
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* DMA Channl/Stream Selections *****************************************************/ |
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/* Stream selections are arbitrary for now but might become important in the future |
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* is we set aside more DMA channels/streams. |
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* |
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* SDIO DMA |
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* DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA |
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* DMAMAP_SDIO_2 = Channel 4, Stream 6 |
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*/ |
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#define DMAMAP_SDIO DMAMAP_SDIO_1 |
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/* LED definitions ******************************************************************/ |
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any |
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* way. The following definitions are used to access individual LEDs. |
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*/ |
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/* LED index values for use with stm32_setled() */ |
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#define BOARD_LED1 0 |
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//#define BOARD_LED2 1 |
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#define BOARD_NLEDS 1 |
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#define BOARD_LED_BLUE BOARD_LED1 |
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//#define BOARD_LED_RED BOARD_LED2 |
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/* LED bits for use with stm32_setleds() */ |
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#define BOARD_LED1_BIT (1 << BOARD_LED1) |
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#define BOARD_LED2_BIT (1 << BOARD_LED2) |
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on board the |
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* omnibusf4sd. The following definitions describe how NuttX controls the LEDs: |
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*/ |
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#define LED_STARTED 0 /* LED1 */ |
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#define LED_HEAPALLOCATE 1 /* LED2 */ |
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#define LED_IRQSENABLED 2 /* LED1 */ |
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#define LED_STACKCREATED 3 /* LED1 + LED2 */ |
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#define LED_INIRQ 4 /* LED1 */ |
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#define LED_SIGNAL 5 /* LED2 */ |
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#define LED_ASSERTION 6 /* LED1 + LED2 */ |
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#define LED_PANIC 7 /* LED1 + LED2 */ |
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/* Alternate function pin selections ************************************************/ |
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/* UART1: |
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* |
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* PA10 (RX) and PA9 (TX) are broken out on J5 |
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*/ |
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#define GPIO_USART1_RX GPIO_USART1_RX_1 |
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#define GPIO_USART1_TX GPIO_USART1_TX_1 |
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/* USART1 require a RX DMA configuration */ |
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#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 |
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/* USART3: |
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* |
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* PC10 (TX) and PC11 (RX) are broken out on J4 |
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* |
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* However, this port is shared with SPI3 which contains the BMP280 and MAX7456 |
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* |
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* The Silkscreen pin labeled SCL is TX |
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* MISO is RX |
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*/ |
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//#define GPIO_USART3_RX GPIO_USART3_RX_2 |
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//#define GPIO_USART3_TX GPIO_USART3_TX_2 |
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/* UART4: |
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* |
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* PA0 (TX) -- Labeled RSSI on the silkscreen is only broken out on a test pad |
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* on the pro version. It's on a 2.54mm header on other versions |
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* PA1 (RX) -- Motor 5 out |
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*/ |
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#define GPIO_UART4_RX GPIO_UART4_RX_1 |
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#define GPIO_UART4_TX GPIO_UART4_TX_1 |
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/* UART6: |
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* |
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* PC6 (TX) and PC7 (RX) are broken out on J10 |
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*/ |
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#define GPIO_USART6_RX GPIO_USART6_RX_1 |
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#define GPIO_USART6_TX GPIO_USART6_TX_1 |
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/* USART6 require a RX DMA configuration */ |
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 |
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/* SPI1: |
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* MPU6000 |
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* CS: PA4 -- configured in board_config.h |
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* CLK: PA5 |
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* MISO: PA6 |
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* MOSI: PA7 |
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*/ |
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 |
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 |
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 |
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/* SPI2: |
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* SD Card |
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* CS: PB12 -- configured in board_config.h |
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* CLK: PB13 |
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* MISO: PB14 |
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* MOSI: PB15 |
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*/ |
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 |
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 |
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 |
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/* SPI3: |
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* BMP280 |
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* CS: PB3 -- configured in board_config.h |
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* CLK: PC10 |
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* MISO: PC11 |
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* MOSI: PC12 |
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*/ |
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_2 |
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_2 |
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2 |
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/* |
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* I2C (external) |
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* |
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* SCL: PB10 |
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* SDA: PB11 |
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* |
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* TODO: |
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* The optional _GPIO configurations allow the I2C driver to manually |
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* reset the bus to clear stuck slaves. They match the pin configuration, |
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* but are normally-high GPIOs. |
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*/ |
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 |
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 |
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// TODO: |
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//#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN6) |
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//#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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#undef EXTERN |
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#if defined(__cplusplus) |
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#define EXTERN extern "C" |
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extern "C" { |
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#else |
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#define EXTERN extern |
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#endif |
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/************************************************************************************ |
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* Public Function Prototypes |
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************************************************************************************/ |
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/************************************************************************************ |
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* Name: stm32_boardinitialize |
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* |
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* Description: |
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* All STM32 architectures must provide the following entry point. This entry point |
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* is called early in the intitialization -- after all memory has been configured |
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* and mapped but before any devices have been initialized. |
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* |
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************************************************************************************/ |
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EXTERN void stm32_boardinitialize(void); |
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/************************************************************************************ |
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* Name: stm32_ledinit, stm32_setled, and stm32_setleds |
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* |
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* Description: |
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* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If |
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* CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to |
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* control the LEDs from user applications. |
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* |
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************************************************************************************/ |
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#ifndef CONFIG_ARCH_LEDS |
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EXTERN void stm32_ledinit(void); |
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EXTERN void stm32_setled(int led, bool ledon); |
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EXTERN void stm32_setleds(uint8_t ledset); |
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#endif |
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#undef EXTERN |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __CONFIG_OMNIBUSF4SD_INCLUDE_BOARD_H */
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