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190 lines
8.1 KiB
190 lines
8.1 KiB
/************************************************************************************ |
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* arch/hc/include/m9s12/irq.h |
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* |
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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/* This file should never be included directed but, rather, |
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* only indirectly through nuttx/irq.h |
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*/ |
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#ifndef __ARCH_HC_INCLUDE_M9S12_IRQ_H |
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#define __ARCH_HC_INCLUDE_M9S12_IRQ_H |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#include <nuttx/irq.h> |
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/************************************************************************************ |
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* Definitions |
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************************************************************************************/ |
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/* IRQ Numbers */ |
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#define HCS12_IRQ_VRESET 0 /* fffe: External reset, power on reset orlow voltage reset */ |
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#define HCS12_IRQ_VCLKMON 1 /* fffc: Clock monitor fail reset */ |
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#define HCS12_IRQ_VCOP 2 /* fffa: COP failure reset*/ |
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#define HCS12_IRQ_VTRAP 3 /* fff8: Unimplemented instruction trap */ |
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#define HCS12_IRQ_VSWI 4 /* fff6: SWI */ |
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#define HCS12_IRQ_VXIRQ 5 /* fff4: XIRQ */ |
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#define HCS12_IRQ_VIRQ 6 /* fff2: IRQ */ |
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#define HCS12_IRQ_VRTI 7 /* fff0: Real-time interrupt */ |
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/* ffe8-ffef: Reserved */ |
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#define HCS12_IRQ_VTIMCH4 8 /* ffe6: Standard timer channel 4 */ |
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#define HCS12_IRQ_VTIMCH5 9 /* ffe4: Standard timer channel 5 */ |
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#define HCS12_IRQ_VTIMCH6 10 /* ffe2: Standard timer channel 6 */ |
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#define HCS12_IRQ_VTIMCH7 11 /* ffe0: Standard timer channel 7 */ |
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#define HCS12_IRQ_VTIMOVF 12 /* ffde: Standard timer overflow */ |
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#define HCS12_IRQ_VTIMPAOVF 13 /* ffdc: Pulse accumulator overflow */ |
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#define HCS12_IRQ_VTIMPAIE 14 /* ffda: Pulse accumulator input edge */ |
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#define HCS12_IRQ_VSPI 15 /* ffd8: SPI */ |
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#define HCS12_IRQ_VSCI0 16 /* ffd6: SCI0 */ |
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#define HCS12_IRQ_VSCI1 17 /* ffd4: SCI1 */ |
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#define HCS12_IRQ_VATD 18 /* ffd2: ATD */ |
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/* ffd0: Reserved */ |
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#define HCS12_IRQ_VPORTJ 19 /* ffce: Port J */ |
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#define HCS12_IRQ_VPORTH 20 /* ffcc: Port H */ |
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#define HCS12_IRQ_VPORTG 21 /* ffca: Port G */ |
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/* ffc8: Reserved */ |
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#define HCS12_IRQ_VCRGPLLLCK 22 /* ffc6: CRG PLL lock */ |
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#define HCS12_IRQ_VCRGSCM 23 /* ffc4: CRG self clock mode */ |
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/* ffc2: Reserved */ |
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#define HCS12_IRQ_VIIC 24 /* ffc0: IIC bus */ |
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/* ffba-ffbf: Reserved */ |
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#define HCS12_IRQ_VFLASH 25 /* ffb8: FLASH */ |
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#define HCS12_IRQ_VEPHY 26 /* ffb6: EPHY interrupt */ |
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#define HCS12_IRQ_VEMACCRXBAC 27 /* ffb4: EMAC receive buffer A complete */ |
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#define HCS12_IRQ_VEMACCRXBBC 28 /* ffb2: EMAC receive buffer B complete */ |
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#define HCS12_IRQ_VEMACTXC 29 /* ffb0: EMAC frame transmission complete */ |
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#define HCS12_IRQ_VEMACRXFC 30 /* ffae: EMAC receive flow control */ |
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#define HCS12_IRQ_VEMACMII 31 /* ffac: EMAC MII management transfer complete */ |
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#define HCS12_IRQ_VEMACRXERR 32 /* ffaa: EMAC receive error */ |
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#define HCS12_IRQ_VEMACRXBAO 33 /* ffa8: EMAC receive buffer A overrun */ |
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#define HCS12_IRQ_VEMACRXBBO 34 /* ffa6: EMAC receive buffer B overrun */ |
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#define HCS12_IRQ_VEMACBRXERR 35 /* ffa4: EMAC babbling receive error */ |
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#define HCS12_IRQ_VEMACLC 36 /* ffa2: EMAC late collision */ |
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#define HCS12_IRQ_VEMACEC 37 /* ffa0: EMAC excessive collision */ |
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/* ff80-ff9f: Reserved */ |
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#define HCS12_IRQ_NVECTORS 38 |
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/* GPIO interrupts. The m9s12x supports several interrupts on PIM ports G, H, |
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* and J. We go through some special efforts to keep the number of IRQs |
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* to a minimum in this sparse interrupt case. |
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* |
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* Port G: Pins 0-7 |
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* Port H: Pins 0-6 |
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* Port J: Pins 0-3 and 6-7 |
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*/ |
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#ifdef CONFIG_GPIO_IRQ |
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/* To conserve space, interrupts must also be configured, port by port */ |
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# define HCC12_IRQ_PGFIRST HCS12_IRQ_NVECTORS |
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# ifdef CONFIG_HCS12_PORTG_INTS |
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# define HCS12_IRQ_PGSET 0xff |
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# define HCS12_IRQ_PG0 (HCC12_IRQ_PGFIRST+0) |
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# define HCS12_IRQ_PG1 (HCC12_IRQ_PGFIRST+1) |
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# define HCS12_IRQ_PG2 (HCC12_IRQ_PGFIRST+2) |
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# define HCS12_IRQ_PG3 (HCC12_IRQ_PGFIRST+3) |
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# define HCS12_IRQ_PG4 (HCC12_IRQ_PGFIRST+4) |
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# define HCS12_IRQ_PG5 (HCC12_IRQ_PGFIRST+5) |
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# define HCS12_IRQ_PG6 (HCC12_IRQ_PGFIRST+6) |
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# define HCS12_IRQ_PG7 (HCC12_IRQ_PGFIRST+7) |
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# define HCC12_IRQ_PHFIRST (HCC12_IRQ_PGFIRST+8) |
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# else |
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# define HCC12_IRQ_PHFIRST HCC12_IRQ_PGFIRST |
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# endif |
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# ifdef CONFIG_HCS12_PORTH_INTS |
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# define HCS12_IRQ_PHSET 0x7f |
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# define HCS12_IRQ_PH0 (HCC12_IRQ_PHFIRST+0) |
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# define HCS12_IRQ_PH1 (HCC12_IRQ_PHFIRST+1) |
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# define HCS12_IRQ_PH2 (HCC12_IRQ_PHFIRST+2) |
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# define HCS12_IRQ_PH3 (HCC12_IRQ_PHFIRST+3) |
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# define HCS12_IRQ_PH4 (HCC12_IRQ_PHFIRST+4) |
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# define HCS12_IRQ_PH5 (HCC12_IRQ_PHFIRST+5) |
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# define HCS12_IRQ_PH6 (HCC12_IRQ_PHFIRST+6) |
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# define HCC12_IRQ_PJFIRST (HCC12_IRQ_PHFIRST+7) |
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# else |
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# define HCC12_IRQ_PJFIRST HCC12_IRQ_PHFIRST |
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# endif |
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# ifdef CONFIG_HCS12_PORTJ_INTS |
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# define HCS12_IRQ_PJSET 0xcf |
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# define HCS12_IRQ_PJ0 (HCC12_IRQ_PJFIRST+0) |
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# define HCS12_IRQ_PJ1 (HCC12_IRQ_PJFIRST+1) |
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# define HCS12_IRQ_PJ2 (HCC12_IRQ_PJFIRST+2) |
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# define HCS12_IRQ_PJ3 (HCC12_IRQ_PJFIRST+3) |
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# define HCS12_IRQ_PJ6 (HCC12_IRQ_PJFIRST+4) |
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# define HCS12_IRQ_PJ7 (HCC12_IRQ_PJFIRST+5) |
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# define HCS12_IRQ_NIRQS (HCC12_IRQ_PJFIRST+6) |
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# else |
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# define HCS12_IRQ_NIRQS HCC12_IRQ_PJFIRST |
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# endif |
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#else |
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# define HCS12_IRQ_NIRQS HCS12_IRQ_NVECTORS |
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#endif /* CONFIG_GPIO_IRQ */ |
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#define HCS12_IRQ_VILLEGAL HCS12_IRQ_NIRQS /* Any reserved vector */ |
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#define NR_IRQS (HCS12_IRQ_NIRQS+1) |
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/************************************************************************************ |
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* Public Types |
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************************************************************************************/ |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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#ifdef __cplusplus |
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#define EXTERN extern "C" |
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extern "C" { |
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#else |
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#define EXTERN extern |
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#endif |
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/************************************************************************************ |
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* Public Functions |
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************************************************************************************/ |
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#undef EXTERN |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif |
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#endif /* __ARCH_HC_INCLUDE_M9S12_IRQ_H */
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