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477 lines
26 KiB
477 lines
26 KiB
/**************************************************************************** |
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* drivers/net/enc28j60.h |
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* |
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* Copyright (C) 2010 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* References: |
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* - ENC28J60 Data Sheet, Stand-Alone Ethernet Controller with SPI Interface, |
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* DS39662C, 2008 Microchip Technology Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************/ |
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#ifndef __DRIVERS_NET_ENC28J60_H |
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#define __DRIVERS_NET_ENC28J60_H |
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/**************************************************************************** |
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* Included Files |
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****************************************************************************/ |
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/**************************************************************************** |
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* Pre-processor Definitions |
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****************************************************************************/ |
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/* ENC28J60 Commands ********************************************************/ |
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/* A total of seven instructions are implemented on the ENC28J60. Where: |
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* |
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* aaaaaa is the 5-bit address of a control register, and |
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* dddddddd is one or more bytes of data that may accompany the command. |
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*/ |
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#define ENC_RCR (0x00) /* Read Control Register |
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* 000 | aaaaa | (Register value returned)) */ |
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#define ENC_RBM (0x3a) /* Read Buffer Memory |
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* 001 | 11010 | (Read buffer data follows) */ |
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#define ENC_WCR (0x40) /* Write Control Register |
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* 010 | aaaaa | dddddddd */ |
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#define ENC_WBM (0x7a) /* Write Buffer Memory |
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* 011 | 11010 | (Write buffer data follows) */ |
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#define ENC_BFS (0x80) /* Bit Field Set |
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* 100 | aaaaa | dddddddd */ |
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#define ENC_BFC (0xa0) /* Bit Field Clear |
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* 101 | aaaaa | dddddddd */ |
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#define ENC_SRC (0xff) /* System Reset |
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* 111 | 11111 | (No data) */ |
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/* Global Control Registers *************************************************/ |
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/* Control registers are accessed with the RCR, RBM, WCR, BFS, and BFC |
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* commands. The following identifies all ENC28J60 control registers. The |
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* control register memory is partitioned into four banks, selectable by the |
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* bank select bits, BSEL1:BSEL0, in the ECON1 register. |
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* |
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* The last five locations (0x1b to 0x1f) of all banks point to a common set |
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* of registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers |
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* used in controlling and monitoring the operation of the device. Their |
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* common mapping allows easy access without switching the bank. |
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* |
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* Control registers for the ENC28J60 are generically grouped as ETH, MAC and |
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* MII registers. Register names starting with E belong to the ETH group. |
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* Similarly, registers names starting with MA belong to the MAC group and |
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* registers prefixed with MI belong to the MII group. |
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*/ |
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#define ENC_EIE (0x1b) /* Ethernet Interrupt Enable Register */ |
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#define ENC_EIR (0x1c) /* Ethernet Interupt Request Register */ |
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#define ENC_ESTAT (0x1d) /* Ethernet Status Register */ |
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#define ENC_ECON2 (0x1e) /* Ethernet Control 2 Register */ |
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#define ENC_ECON1 (0x1f) /* Ethernet Control 1 Register */ |
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/* Ethernet Interrupt Enable Register Bit Definitions */ |
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#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */ |
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#define EIE_TXERIE (1 << 1) /* Bit 1: Transmit Error Interrupt Enable */ |
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/* Bit 2: Reserved */ |
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#define EIE_TXIE (1 << 3) /* Bit 3: Transmit Enable */ |
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#define EIE_LINKIE (1 << 4) /* Bit 4: Link Status Change Interrupt Enable */ |
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#define EIE_DMAIE (1 << 5) /* Bit 5: DMA Interrupt Enable */ |
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#define EIE_PKTIE (1 << 6) /* Bit 6: Receive Packet Pending Interrupt Enable */ |
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#define EIE_INTIE (1 << 7) /* Bit 7: Global INT Interrupt Enable */ |
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/* Ethernet Interrupt Request Register Bit Definitions */ |
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#define EIR_RXERIF (1 << 0) /* Bit 0: Receive Error Interrupt */ |
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#define EIR_TXERIF (1 << 1) /* Bit 1: Transmit Error Interrupt */ |
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/* Bit 2: Reserved */ |
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#define EIR_TXIF (1 << 3) /* Bit 3: Transmit Interrupt */ |
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#define EIR_LINKIF (1 << 4) /* Bit 4: Link Change Interrupt */ |
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#define EIR_DMAIF (1 << 5) /* Bit 5: DMA Interrupt */ |
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#define EIR_PKTIF (1 << 6) /* Bit 6: Receive Packet Pending Interrupt */ |
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/* Bit 7: Reserved */ |
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#define EIR_ALLINTS (0x7b) /* All interrupts */ |
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/* Ethernet Status Register Bit Definitions */ |
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#define ESTAT_CLKRDY (1 << 0) /* Bit 0: Clock Ready */ |
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#define ESTAT_TXABRT (1 << 1) /* Bit 1: Transmit Abort Error */ |
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#define ESTAT_RXBUSY (1 << 2) /* Bit 2: Receive Busy */ |
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/* Bit 3: Reserved */ |
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#define ESTAT_LATECOL (1 << 4) /* Bit 4: Late Collision Error */ |
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/* Bit 5: Reserved */ |
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#define ESTAT_BUFER (1 << 6) /* Bit 6: Ethernet Buffer Error Status */ |
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#define ESTAT_INT (1 << 7) /* Bit 7: INT Interrupt */ |
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/* Ethernet Control 1 Register Bit Definitions */ |
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#define ECON1_BSEL_SHIFT (0) /* Bits 0-1: Bank select */ |
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#define ECON1_BSEL_MASK (3 << ECON1_BSEL_SHIFT) |
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# define ECON1_BSEL_BANK0 (0 << ECON1_BSEL_SHIFT) /* Bank 0 */ |
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# define ECON1_BSEL_BANK1 (1 << ECON1_BSEL_SHIFT) /* Bank 1 */ |
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# define ECON1_BSEL_BANK2 (2 << ECON1_BSEL_SHIFT) /* Bank 2 */ |
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# define ECON1_BSEL_BANK3 (3 << ECON1_BSEL_SHIFT) /* Bank 3 */ |
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#define ECON1_RXEN (1 << 2) /* Bit 2: Receive Enable */ |
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#define ECON1_TXRTS (1 << 3) /* Bit 3: Transmit Request to Send */ |
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#define ECON1_CSUMEN (1 << 4) /* Bit 4: DMA Checksum Enable */ |
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#define ECON1_DMAST (1 << 5) /* Bit 5: DMA Start and Busy Status */ |
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#define ECON1_RXRST (1 << 6) /* Bit 6: Receive Logic Reset */ |
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#define ECON1_TXRST (1 << 7) /* Bit 7: Transmit Logic Reset */ |
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/* Ethernet Control 2 Register */ |
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/* Bits 0-2: Reserved */ |
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#define ECON2_VRPS (1 << 3) /* Bit 3: Voltage Regulator Power Save Enable */ |
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/* Bit 4: Reserved */ |
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#define ECON2_PWRSV (1 << 5) /* Bit 5: Power Save Enable */ |
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#define ECON2_PKTDEC (1 << 6) /* Bit 6: Packet Decrement */ |
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#define ECON2_AUTOINC (1 << 7) /* Bit 7: Automatic Buffer Pointer Increment Enable */ |
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/* Banked Control Registers *************************************************/ |
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/* The remaining control registers are identified with a a 5 bit address and |
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* a bank selection. We pack the bank number and an indication if this is |
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* a MAC/PHY register access together with the control register address |
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* together to keep the design simpler. |
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*/ |
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#define ENC_ADDR_SHIFT (0) /* Bits 0-4: Register address */ |
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#define ENC_ADDR_MASK (0x1f << ENC_ADDR_SHIFT) |
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#define ENC_BANK_SHIFT (5) /* Bits 5-6: Bank number */ |
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#define ENC_BANK_MASK (3 << ENC_BSEL_SHIFT) |
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# define ENC_BANK0 (0 << ENC_BSEL_SHIFT) |
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# define ENC_BANK1 (1 << ENC_BSEL_SHIFT) |
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# define ENC_BANK2 (2 << ENC_BSEL_SHIFT) |
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# define ENC_BANK3 (3 << ENC_BSEL_SHIFT) |
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#define ENC_PHYMAC_SHIFT (7) /* Bit 7: This is a PHY/MAC command */ |
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#define ENC_PHYMAC (1 << ENC_PHYMAC_SHIFT) |
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#define REGADDR(a,b,m) ((m) << ENC_PHYMAC_SHIFT | (b) << ENC_BANK_SHIFT | (a)) |
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#define GETADDR(a) ((a) & ENC_ADDR_MASK) |
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#define GETBANK(a) (((a) >> ENC_BANK_SHIFT) & 3) |
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#define ISPHYMAC(a) (((a) & ENC_PHYMAC) != 0) |
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/* Bank 0 Control Register Addresses */ |
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#define ENC_ERDPTL REGADDR(0x00, 0, 0) /* Read Pointer Low Byte (ERDPT<7:0> */ |
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#define ENC_ERDPTH REGADDR(0x01, 0, 0) /* Read Pointer High Byte (ERDPT<12:8>) */ |
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#define ENC_EWRPTL REGADDR(0x02, 0, 0) /* Write Pointer Low Byte (EWRPT<7:0>) */ |
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#define ENC_EWRPTH REGADDR(0x03, 0, 0) /* Write Pointer High Byte (EWRPT<12:8>) */ |
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#define ENC_ETXSTL REGADDR(0x04, 0, 0) /* TX Start Low Byte (ETXST<7:0>) */ |
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#define ENC_ETXSTH REGADDR(0x05, 0, 0) /* TX Start High Byte (ETXST<12:8>) */ |
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#define ENC_ETXNDL REGADDR(0x06, 0, 0) /* TX End Low Byte (ETXND<7:0>) */ |
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#define ENC_ETXNDH REGADDR(0x07, 0, 0) /* TX End High Byte (ETXND<12:8>) */ |
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#define ENC_ERXSTL REGADDR(0x08, 0, 0) /* RX Start Low Byte (ERXST<7:0>) */ |
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#define ENC_ERXSTH REGADDR(0x09, 0, 0) /* RX Start High Byte (ERXST<12:8>) */ |
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#define ENC_ERXNDL REGADDR(0x0a, 0, 0) /* RX End Low Byte (ERXND<7:0>) */ |
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#define ENC_ERXNDH REGADDR(0x0b, 0, 0) /* RX End High Byte (ERXND<12:8>) */ |
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#define ENC_ERXRDPTL REGADDR(0x0c, 0, 0) /* RX RD Pointer Low Byte (ERXRDPT<7:0>) */ |
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#define ENC_ERXRDPTH REGADDR(0x0d, 0, 0) /* RX RD Pointer High Byte (ERXRDPT<12:8>) */ |
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#define ENC_ERXWRPTL REGADDR(0x0e, 0, 0) /* RX WR Pointer Low Byte (ERXWRPT<7:0>) */ |
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#define ENC_ERXWRPTH REGADDR(0x0f, 0, 0) /* RX WR Pointer High Byte (ERXWRPT<12:8>) */ |
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#define ENC_EDMASTL REGADDR(0x10, 0, 0) /* DMA Start Low Byte (EDMAST<7:0>) */ |
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#define ENC_EDMASTH REGADDR(0x11, 0, 0) /* DMA Start High Byte (EDMAST<12:8>) */ |
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#define ENC_EDMANDL REGADDR(0x12, 0, 0) /* DMA End Low Byte (EDMAND<7:0>) */ |
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#define ENC_EDMANDH REGADDR(0x13, 0, 0) /* DMA End High Byte (EDMAND<12:8>) */ |
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#define ENC_EDMADSTL REGADDR(0x14, 0, 0) /* DMA Destination Low Byte (EDMADST<7:0>) */ |
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#define ENC_EDMADSTH REGADDR(0x15, 0, 0) /* DMA Destination High Byte (EDMADST<12:8>) */ |
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#define ENC_EDMACSL REGADDR(0x16, 0, 0) /* DMA Checksum Low Byte (EDMACS<7:0>) */ |
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#define ENC_EDMACSH REGADDR(0x17, 0, 0) /* DMA Checksum High Byte (EDMACS<15:8>) */ |
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/* 0x18-0x1a: Reserved */ |
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */ |
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/* Bank 1 Control Register Addresses */ |
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#define ENC_EHT0 REGADDR(0x00, 1, 0) /* Hash Table Byte 0 (EHT<7:0>) */ |
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#define ENC_EHT1 REGADDR(0x01, 1, 0) /* Hash Table Byte 1 (EHT<15:8>) */ |
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#define ENC_EHT2 REGADDR(0x02, 1, 0) /* Hash Table Byte 2 (EHT<23:16>) */ |
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#define ENC_EHT3 REGADDR(0x03, 1, 0) /* Hash Table Byte 3 (EHT<31:24>) */ |
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#define ENC_EHT4 REGADDR(0x04, 1, 0) /* Hash Table Byte 4 (EHT<39:32>) */ |
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#define ENC_EHT5 REGADDR(0x05, 1, 0) /* Hash Table Byte 5 (EHT<47:40>) */ |
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#define ENC_EHT6 REGADDR(0x06, 1, 0) /* Hash Table Byte 6 (EHT<55:48>) */ |
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#define ENC_EHT7 REGADDR(0x07, 1, 0) /* Hash Table Byte 7 (EHT<63:56>) */ |
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#define ENC_EPMM0 REGADDR(0x08, 1, 0) /* Pattern Match Mask Byte 0 (EPMM<7:0>) */ |
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#define ENC_EPMM1 REGADDR(0x09, 1, 0) /* Pattern Match Mask Byte 1 (EPMM<15:8>) */ |
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#define ENC_EPMM2 REGADDR(0x0a, 1, 0) /* Pattern Match Mask Byte 2 (EPMM<23:16>) */ |
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#define ENC_EPMM3 REGADDR(0x0b, 1, 0) /* Pattern Match Mask Byte 3 (EPMM<31:24>) */ |
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#define ENC_EPMM4 REGADDR(0x0c, 1, 0) /* Pattern Match Mask Byte 4 (EPMM<39:32>) */ |
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#define ENC_EPMM5 REGADDR(0x0d, 1, 0) /* Pattern Match Mask Byte 5 (EPMM<47:40>) */ |
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#define ENC_EPMM6 REGADDR(0x0e, 1, 0) /* Pattern Match Mask Byte 6 (EPMM<55:48>) */ |
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#define ENC_EPMM7 REGADDR(0x0f, 1, 0) /* Pattern Match Mask Byte 7 (EPMM<63:56>) */ |
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#define ENC_EPMCSL REGADDR(0x10, 1, 0) /* Pattern Match Checksum Low Byte (EPMCS<7:0>) */ |
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#define ENC_EPMCSH REGADDR(0x11, 1, 0) /* Pattern Match Checksum High Byte (EPMCS<15:0>) */ |
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/* 0x12-0x13: Reserved */ |
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#define ENC_EPMOL REGADDR(0x14, 1, 0) /* Pattern Match Offset Low Byte (EPMO<7:0>) */ |
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#define ENC_EPMOH REGADDR(0x15, 1, 0) /* Pattern Match Offset High Byte (EPMO<12:8>) */ |
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/* 0x16-0x17: Reserved */ |
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#define ENC_ERXFCON REGADDR(0x18, 1, 0) /* Receive Filter Configuration */ |
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#define ENC_EPKTCNT REGADDR(0x19, 1, 0) /* Ethernet Packet Count */ |
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/* 0x1a: Reserved */ |
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */ |
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/* Receive Filter Configuration Bit Definitions */ |
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#define ERXFCON_BCEN (1 << 0) /* Bit 0: Broadcast Filter Enable */ |
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#define ERXFCON_MCEN (1 << 1) /* Bit 1: Multicast Filter Enable */ |
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#define ERXFCON_HTEN (1 << 2) /* Bit 2: Hash Table Filter Enable */ |
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#define ERXFCON_MPEN (1 << 3) /* Bit 3: Magic Packet Filter Enable */ |
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#define ERXFCON_PMEN (1 << 4) /* Bit 4: Pattern Match Filter Enable */ |
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#define ERXFCON_CRCEN (1 << 5) /* Bit 5: Post-Filter CRC Check Enable */ |
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#define ERXFCON_ANDOR (1 << 6) /* Bit 6: AND/OR Filter Select */ |
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#define ERXFCON_UCEN (1 << 7) /* Bit 7: Unicast Filter Enable */ |
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/* Bank 2 Control Register Addresses */ |
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#define ENC_MACON1 REGADDR(0x00, 2, 1) /* MAC Control 1 */ |
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/* 0x01: Reserved */ |
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#define ENC_MACON3 REGADDR(0x02, 2, 1) /* MAC Control 3 */ |
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#define ENC_MACON4 REGADDR(0x03, 2, 1) /* MAC Control 4 */ |
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#define ENC_MABBIPG REGADDR(0x04, 2, 1) /* Back-to-Back Inter-Packet Gap (BBIPG<6:0>) */ |
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/* 0x05: Reserved */ |
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#define ENC_MAIPGL REGADDR(0x06, 2, 1) /* Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) */ |
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#define ENC_MAIPGH REGADDR(0x07, 2, 1) /* Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) */ |
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#define ENC_MACLCON1 REGADDR(0x08, 2, 1) /* MAC Collision Control 1 */ |
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#define ENC_MACLCON2 REGADDR(0x09, 2, 1) /* MAC Collision Control 2 */ |
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#define ENC_MAMXFLL REGADDR(0x0a, 2, 1) /* Maximum Frame Length Low Byte (MAMXFL<7:0>) */ |
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#define ENC_MAMXFLH REGADDR(0x0b, 2, 1) /* Maximum Frame Length High Byte (MAMXFL<15:8>) */ |
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/* 0x0c-0x11: Reserved */ |
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#define ENC_MICMD REGADDR(0x12, 2, 1) /* MII Command Register */ |
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/* 0x13: Reserved */ |
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#define ENC_MIREGADR REGADDR(0x14, 2, 1) /* MII Register Address */ |
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/* 0x15: Reserved */ |
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#define ENC_MIWRL REGADDR(0x16, 2, 1) /* MII Write Data Low Byte (MIWR<7:0>) */ |
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#define ENC_MIWRH REGADDR(0x17, 2, 1) /* MII Write Data High Byte (MIWR<15:8>) */ |
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#define ENC_MIRDL REGADDR(0x18, 2, 1) /* MII Read Data Low Byte (MIRD<7:0>) */ |
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#define ENC_MIRDH REGADDR(0x19, 2, 1) /* MII Read Data High Byte(MIRD<15:8>) */ |
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/* 0x1a: Reserved */ |
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */ |
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/* MAC Control 1 Register Bit Definitions */ |
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#define MACON1_MARXEN (1 << 0) /* Bit 0: MAC Receive Enable */ |
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#define MACON1_PASSALL (1 << 1) /* Bit 1: Pass All Received Frames Enable */ |
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#define MACON1_RXPAUS (1 << 2) /* Bit 2: Pause Control Frame Reception Enable */ |
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#define MACON1_TXPAUS (1 << 3) /* Bit 3: Pause Control Frame Transmission Enable */ |
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/* Bits 4-7: Unimplemented or reserved */ |
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/* MAC Control 1 Register Bit Definitions */ |
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#define MACON3_FULDPX (1 << 0) /* Bit 0: MAC Full-Duplex Enable */ |
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#define MACON3_FRMLNEN (1 << 1) /* Bit 1: Frame Length Checking Enable */ |
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#define MACON3_HFRMLEN (1 << 2) /* Bit 2: Huge Frame Enable */ |
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#define MACON3_PHDRLEN (1 << 3) /* Bit 3: Proprietary Header Enable */ |
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#define MACON3_TXCRCEN (1 << 4) /* Bit 4: Transmit CRC Enable */ |
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#define MACON3_PADCFG0 (1 << 5) /* Bit 5: Automatic Pad and CRC Configuration */ |
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#define MACON3_PADCFG1 (1 << 6) /* Bit 6: " " " " " " " " " " */ |
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#define MACON3_PADCFG2 (1 << 7) /* Bit 7: " " " " " " " " " " */ |
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/* MAC Control 1 Register Bit Definitions */ |
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#define MACON4_NOBKOFF (1 << 4) /* Bit 4: No Backoff Enable */ |
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#define MACON4_BPEN (1 << 5) /* Bit 5: No Backoff During Backpressure Enable */ |
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#define MACON4_DEFER (1 << 6) /* Bit 6: Defer Transmission Enable bit */ |
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/* MII Command Register Bit Definitions */ |
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#define MICMD_MIIRD (1 << 0) /* Bit 0: MII Read Enable */ |
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#define MICMD_MIISCAN (1 << 1) /* Bit 1: MII Scan Enable */ |
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/* Bank 3 Control Register Addresses */ |
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#define ENC_MAADR5 REGADDR(0x00, 3, 1) /* MAC Address Byte 5 (MAADR<15:8>) */ |
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#define ENC_MAADR6 REGADDR(0x01, 3, 1) /* MAC Address Byte 6 (MAADR<7:0>) */ |
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#define ENC_MAADR3 REGADDR(0x02, 3, 1) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */ |
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#define ENC_MAADR4 REGADDR(0x03, 3, 1) /* MAC Address Byte 4 (MAADR<23:16>) */ |
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#define ENC_MAADR1 REGADDR(0x04, 3, 1) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */ |
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#define ENC_MAADR2 REGADDR(0x05, 3, 1) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2 */ |
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#define ENC_EBSTSD REGADDR(0x06, 3, 0) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */ |
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#define ENC_EBSTCON REGADDR(0x07, 3, 0) /* Built-in Self-Test Control */ |
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#define ENC_EBSTCSL REGADDR(0x08, 3, 0) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */ |
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#define ENC_EBSTCSH REGADDR(0x09, 3, 0) /* Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) */ |
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#define ENC_MISTAT REGADDR(0x0a, 3, 1) /* MII Status Register */ |
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/* 0x0b-0x11: Reserved */ |
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#define ENC_EREVID REGADDR(0x12, 3, 0) /* Ethernet Revision ID */ |
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/* 0x13-0x14: Reserved */ |
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#define ENC_ECOCON REGADDR(0x15, 3, 0) /* Clock Output Control */ |
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/* 0x16: Reserved */ |
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#define ENC_EFLOCON REGADDR(0x17, 3, 0) /* Ethernet Flow Control */ |
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#define ENC_EPAUSL REGADDR(0x18, 3, 0) /* Pause Timer Value Low Byte (EPAUS<7:0>) */ |
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#define ENC_EPAUSH REGADDR(0x19, 3, 0) /* Pause Timer Value High Byte (EPAUS<15:8>) */ |
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/* 0x1a: Reserved */ |
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */ |
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/* Built-in Self-Test Control Register Bit Definitions */ |
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#define EBSTCON_BISTST (1 << 0) /* Bit 0: Built-in Self-Test Start/Busy */ |
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#define EBSTCON_TME (1 << 1) /* Bit 1: Test Mode Enable */ |
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#define EBSTCON_TMSEL0 (1 << 2) /* Bit 2: Test Mode Select */ |
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#define EBSTCON_TMSEL1 (1 << 3) /* Bit 3: " " " " " " */ |
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#define EBSTCON_PSEL (1 << 4) /* Bit 4: Port Select */ |
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#define EBSTCON_PSV0 (1 << 5) /* Bit 5: Pattern Shift Value */ |
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#define EBSTCON_PSV1 (1 << 6) /* Bit 6: " " " " " */ |
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#define EBSTCON_PSV2 (1 << 7) /* Bit 7: " " " " " */ |
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/* MII Status Register Register Bit Definitions */ |
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#define MISTAT_BUSY (1 << 0) /* Bit 0: MII Management Busy */ |
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#define MISTAT_SCAN (1 << 1) /* Bit 1: MII Management Scan Operation */ |
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#define MISTAT_NVALID (1 << 2) /* Bit 2: MII Management Read Data Not Valid */ |
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/* Bits 3-7: Reserved or unimplemented */ |
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/* Ethernet Flow Control Register Bit Definitions */ |
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#define EFLOCON_FCEN0 (1 << 0) /* Bit 0: Flow Control Enable */ |
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#define EFLOCON_FCEN1 (1 << 1) /* Bit 1: " " " " " " */ |
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#define EFLOCON_FULDPXS (1 << 2) /* Bit 2: Read-Only MAC Full-Duplex Shadow */ |
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/* Bits 3-7: Reserved or unimplemented */ |
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/* PHY Registers ************************************************************/ |
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#define ENC_PHCON1 (0x00) /* PHY Control Register 1 */ |
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#define ENC_PHSTAT1 (0x01) /* PHY Status 1 */ |
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#define ENC_PHID1 (0x02) /* PHY ID Register 1 */ |
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#define ENC_PHID2 (0x03) /* PHY ID Register 2 */ |
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#define ENC_PHCON2 (0x10) /* PHY Control Register 2 */ |
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#define ENC_PHSTAT2 (0x11) /* PHY Status 2 */ |
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#define ENC_PHIE (0x12) /* PHY Interrupt Enable Register */ |
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#define ENC_PHIR (0x13) /* PHY Interrupt Request Register */ |
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#define ENC_PHLCON (0x14) |
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/* PHY Control Register 1 Register Bit Definitions */ |
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#define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Duplex Mode */ |
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#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power-Down */ |
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#define PHCON1_PLOOPBK (1 << 14) /* Bit 14: PHY Loopback */ |
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#define PHCON1_PRST (1 << 15) /* Bit 15: PHY Software Reset */ |
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/* PHY Status 1 Register Bit Definitions */ |
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#define PHSTAT1_JBSTAT (1 << 1) /* Bit 1: PHY Latching Jabber Status */ |
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#define PHSTAT1_LLSTAT (1 << 2) /* Bit 2: PHY Latching Link Status */ |
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#define PHSTAT1_PHDPX (1 << 11) /* Bit 11: PHY Half-Duplex Capable */ |
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#define PHSTAT1_PFDPX (1 << 12) /* Bit 12: PHY Full-Duplex Capable */ |
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/* PHY Control Register 2 Register Bit Definitions */ |
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#define PHCON2_HDLDIS (1 << 8) /* Bit 8: PHY Half-Duplex Loopback Disable */ |
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#define PHCON2_JABBER (1 << 10) /* Bit 10: Jabber Correction Disable */ |
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#define PHCON2_TXDIS (1 << 13) /* Bit 13: Twisted-Pair Transmitter Disable */ |
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#define PHCON2_FRCLINK (1 << 14) /* Bit 14: PHY Force Linkup */ |
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/* PHY Status 2 Register Bit Definitions */ |
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#define PHSTAT2_PLRITY (1 << 5) /* Bit 5: Polarity Status */ |
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#define PHSTAT2_DPXSTAT (1 << 9) /* Bit 9: PHY Duplex Status */ |
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#define PHSTAT2_LSTAT (1 << 10) /* Bit 10: PHY Link Status */ |
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#define PHSTAT2_COLSTAT (1 << 11) /* Bit 11: PHY Collision Status */ |
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#define PHSTAT2_RXSTAT (1 << 12) /* Bit 12: PHY Receive Status */ |
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#define PHSTAT2_TXSTAT (1 << 13) /* Bit 13: PHY Transmit Status */ |
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/* PHY Interrupt Enable Register Bit Definitions */ |
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#define PHIE_PGEIE (1 << 1) /* Bit 1: PHY Global Interrupt Enable */ |
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#define PHIE_PLNKIE (1 << 4) /* Bit 4: PHY Link Change Interrupt Enable */ |
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/* PHIR Regiser Bit Definitions */ |
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#define PHIR_PGIF (1 << 2) /* Bit 2: PHY Global Interrupt */ |
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#define PHIR_PLNKIF (1 << 4) /* Bit 4: PHY Link Change Interrupt */ |
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/* PHLCON Regiser Bit Definitions */ |
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/* Bit 0: Reserved */ |
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#define PHLCON_STRCH (1 << 1) /* Bit 1: LED Pulse Stretching Enable */ |
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#define PHLCON_LFRQ0 (1 << 2) /* Bit 2: LED Pulse Stretch Time Configuration */ |
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#define PHLCON_LFRQ1 (1 << 3) /* Bit 3: " " " " " " " " " */ |
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#define PHLCON_LBCFG0 (1 << 4) /* Bit 4: LEDB Configuration */ |
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#define PHLCON_LBCFG1 (1 << 5) /* Bit 5: " " " " */ |
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#define PHLCON_LBCFG2 (1 << 6) /* Bit 6: " " " " */ |
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#define PHLCON_LBCFG3 (1 << 7) /* Bit 7: " " " " */ |
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#define PHLCON_LACFG0 (1 << 8) /* Bit 8: LEDA Configuration */ |
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#define PHLCON_LACFG1 (1 << 9) /* Bit 9: " " " " */ |
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#define PHLCON_LACFG2 (1 << 10) /* Bit 10: " " " " */ |
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#define PHLCON_LACFG3 (1 << 11) /* Bit 11: " " " " */ |
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/* Packet Memory ************************************************************/ |
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/* 8-Kbyte Transmit/Receive Packet Dual Port SRAM */ |
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#define PKTMEM_START 0x0000 |
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#define PKTMEM_END 0x1fff |
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/* Ethernet frames are between 64 and 1518 bytes long */ |
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#define MIN_FRAMELEN 64 |
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#define MAX_FRAMELEN 1518 |
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/* Packet Control Bits Definitions ******************************************/ |
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#define PKTCTRL_POVERRIDE (1 << 0) /* Bit 0: Per Packet Override */ |
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#define PKTCTRL_PCRCEN (1 << 1) /* Bit 1: Per Packet CRC Enable */ |
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#define PKTCTRL_PPADEN (1 << 2) /* Bit 2: Per Packet Padding Enable */ |
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#define PKTCTRL_PHUGEEN (1 << 3) /* Bit 3: Per Packet Huge Frame Enable */ |
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/* RX Status Bit Definitions ************************************************/ |
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#define RXSTAT_LDEVENT (1 << 0) /* Bit 0: Long event or pack dropped */ |
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/* Bit 1: Reserved */ |
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#define RXSTAT_CEPS (1 << 2) /* Bit 2: Carrier event previously seen */ |
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/* Bit 3: Reserved */ |
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#define RXSTAT_CRCERROR (1 << 4) /* Bit 4: Frame CRC field bad */ |
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#define RXSTAT_LENERROR (1 << 5) /* Bit 5: Packet length != data length */ |
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#define RXSTAT_LENRANGE (1 << 6) /* Bit 6: Type/length field > 1500 bytes */ |
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#define RXSTAT_OK (1 << 7) /* Bit 7: Packet with valid CRC and no symbol errors */ |
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#define RXSTAT_MCAST (1 << 8) /* Bit 8: Packet with multicast address */ |
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#define RXSTAT_BCAST (1 << 9) /* Bit 9: Packet with broadcast address */ |
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#define RXSTAT_DRIBBLE (1 << 10) /* Bit 10: Additional bits received after packet */ |
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#define RXSTAT_CTRLFRAME (1 << 11) /* Bit 11: Control frame with valid type/length */ |
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#define RXSTAT_PAUSE (1 << 12) /* Bit 12: Control frame with pause frame opcde */ |
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#define RXSTAT_UNKOPCODE (1 << 13) /* Bit 13: Control frame with unknown opcode */ |
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#define RXSTAT_VLANTYPE (1 << 14) /* Bit 14: Current frame is a VLAN tagged frame */ |
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/* Bit 15: Zero */ |
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/**************************************************************************** |
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* Public Types |
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****************************************************************************/ |
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/**************************************************************************** |
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* Public Data |
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****************************************************************************/ |
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#ifdef __cplusplus |
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#define EXTERN extern "C" |
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extern "C" { |
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#else |
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#define EXTERN extern |
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#endif |
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/**************************************************************************** |
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* Public Function Prototypes |
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****************************************************************************/ |
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#undef EXTERN |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __DRIVERS_NET_ENC28J60_H */
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