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/**************************************************************************** |
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* arch/z80/include/z180/chip.h |
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* arch/chip/io.h |
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* |
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* Copyright (C) 2012 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************/ |
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#ifndef __ARCH_Z80_INCLUDE_Z180_CHIP_H |
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#define __ARCH_Z80_INCLUDE_Z180_CHIP_H |
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/**************************************************************************** |
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* Included Files |
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****************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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/**************************************************************************** |
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* Pre-processor Definitions |
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****************************************************************************/ |
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/* Bits in the Z180 FLAGS register ******************************************/ |
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#define Z180_C_FLAG 0x01 /* Bit 0: Carry flag */ |
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#define Z180_N_FLAG 0x02 /* Bit 1: Add/Subtract flag */ |
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#define Z180_PV_FLAG 0x04 /* Bit 2: Parity/Overflow flag */ |
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#define Z180_H_FLAG 0x10 /* Bit 4: Half carry flag */ |
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#define Z180_Z_FLAG 0x40 /* Bit 5: Zero flag */ |
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#define Z180_S_FLAG 0x80 /* Bit 7: Sign flag */ |
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/* Z180 Chip Definitions ****************************************************/ |
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/* Z800180 |
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* |
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* The 8-bit Z80180 MPU provides the benefits of reduced system costs and |
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* also provides full backward compatibility with existing ZiLOG Z80 devices. |
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* Reduced system costs are obtained by incorporating several key system |
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* functions on-chip with the CPU. These key functions include I/O devices |
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* such as DMA, UART, and timer channels. Also included on-chip are wait- |
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* state generators, a clock oscillator, and an interrupt controller. The |
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* Z80180 MPU is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages. |
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* |
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* Z80180 Features |
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* |
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* Enhanced Z80 CPU |
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* 1 MB MMU |
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* 2 DMA channels* |
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* 2 UARTs* (up to 512 Kbps) |
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* Two 16-Bit Timers |
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* Clock Serial I/O |
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* On-Chip Oscillator |
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* Power-Down Mode* |
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* Divide-by-One/Divide-by-Two/Multiply-by-Two Clock Options* |
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* Programmable Driver Strength for EMI Tuning |
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* |
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* * Enhanced on the Z8S180 and Z8L180 MPUs |
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*/ |
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#if defined(CONFIG_ARCH_CHIP_Z8018006VSG) || /* 68-pin PLCC */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018010VSG) || /* 68-pin PLCC */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018008VSG) || /* 68-pin PLCC */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018010FSG) || /* 80-pin QFP (11 pins N/C) */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018008VEG) || /* 68-pin PLCC */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018006VEG) /* 68-pin PLCC */ |
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */ |
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# define HAVE_Z8X180 1 /* Z8x180 registers */ |
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# undef HAVE_Z8X181 /* Z8x181 registers */ |
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# undef HAVE_Z8X182 /* Z8x182 registers */ |
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# define HAVE ROM 0 /* No on-chip ROM */ |
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */ |
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# undef HAVE_WDT /* No Watchdog timer */ |
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# define HAVE_NTIMERS16 2 /* Two (2) 16-bit timers */ |
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# define HAVE_NCTCS 0 /* No Counter/Timers (CTCs) */ |
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# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
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# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
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# define HAVE_NSCC 0 /* No serial communication controller */ |
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# define HAVE_NESCC 0 /* No Enhanced Serial Communication Controllers */ |
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# undef HAVE_16550 /* No 16550 MIMIC */ |
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# define HAVE_NIOLINES 0 /* No I/O lines */ |
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# define HAVE_NPAR8 0 /* No 8-bit parallel ports */ |
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# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ |
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#elif defined(CONFIG_ARCH_CHIP_Z8018006PSG) || /* 64-pin DIP 6 MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018008FSG) || /* 80-pin QFP (11 pins N/C) 8MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018010PSG) || /* 64-pin DIP 10MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018006PEG) || /* 64-pin DIP 6MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018010VEG) || /* 68-pin PLCC 10MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018010PEG) || /* 64-pin DIP 10MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018008PSG) || /* 64-pin DIP 8MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018006FSG) /* 80-pin QFP (11 pins N/C) 6MHz 5V */ |
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */ |
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# define HAVE_Z8X180 1 /* Z8x180 registers */ |
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# undef HAVE_Z8X181 /* Z8x181 registers */ |
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# undef HAVE_Z8X182 /* Z8x182 registers */ |
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# define HAVE ROM 0 /* No on-chip ROM */ |
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# undef HAVE_SERIALIO /* No clocked serial I/O ? */ |
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# undef HAVE_WDT /* No Watchdog timer */ |
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# define HAVE_NTIMERS16 2 /* Two (2) 16-bit timers */ |
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# define HAVE_NCTCS 0 /* No Counter/Timers (CTCs) */ |
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# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
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# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
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# define HAVE_NSCC 0 /* No serial communication controller */ |
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# define HAVE_NESCC 0 /* No Enhanced Serial Communication Controllers */ |
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# undef HAVE_16550 /* No 16550 MIMIC */ |
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# define HAVE_NIOLINES 0 /* No I/O lines */ |
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# define HAVE_NPAR8 0 /* No 8-bit parallel ports */ |
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# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ |
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#elif defined(CONFIG_ARCH_CHIP_Z8018000XSO) |
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defined(CONFIG_ARCH_CHIP_Z8018010FEG) |
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defined(CONFIG_ARCH_CHIP_Z8018000WSO) |
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defined(CONFIG_ARCH_CHIP_Z8018008PEG) |
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */ |
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# define HAVE_Z8X180 1 /* Z8x180 registers */ |
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# undef HAVE_Z8X181 /* Z8x181 registers */ |
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# undef HAVE_Z8X182 /* Z8x182 registers */ |
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# define HAVE ROM 0 /* No on-chip ROM */ |
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */ |
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# undef HAVE_WDT /* No Watchdog timer */ |
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# define HAVE_NTIMERS16 2 /* Two (2) 16-bit timers */ |
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# define HAVE_NCTCS 0 /* No Counter/Timers (CTCs) */ |
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# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
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# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
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# define HAVE_NSCC 0 /* No serial communication controller */ |
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# define HAVE_NESCC 0 /* No Enhanced Serial Communication Controllers */ |
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# undef HAVE_16550 /* No 16550 MIMIC */ |
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# define HAVE_NIOLINES 0 /* No I/O lines */ |
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# define HAVE_NPAR8 0 /* No 8-bit parallel ports */ |
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# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ |
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/* Z80181 |
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* |
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* The Z80181 SAC Smart Access Controller is an 8-bit CMOS microprocessor that |
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* combines a Z180-compatible MPU, one channel of the Z85C30 Serial Communications |
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* Controller, a Z80 CTC, two 8-bit general-purpose parallel ports, and two Chip |
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* Select signals, into a single 100-pin Quad Flat Pack package. |
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* |
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* Z80181 Features |
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* |
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* Enhanced Z80 CPU |
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* 1 MB MMU |
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* 2 DMAs |
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* 2 UARTs |
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* Two 16-Bit Timers |
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* Clock Serial I/O |
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* 1 Channel SCC |
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* 1 8-Bit Counter/Timer |
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* 16 I/O Lines |
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* Emulation Mode |
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*/ |
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#elif defined(CONFIG_ARCH_CHIP_Z8018110FEG) /* 100-pin QFP */ |
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */ |
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# undef HAVE_Z8X180 /* Z8x180 registers */ |
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# define HAVE_Z8X181 1 /* Z8x181 registers */ |
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# undef HAVE_Z8X182 /* Z8x182 registers */ |
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# define HAVE ROM 0 /* No on-chip ROM */ |
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */ |
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# undef HAVE_WDT /* No Watchdog timer */ |
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# define HAVE_NTIMERS16 2 /* Two (2) 16-bit timers */ |
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# define HAVE_NCTCS 1 /* One (1) 8-bit counter/timer */ |
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# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
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# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
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# define HAVE_NSCC 1 /* One (1) Z85C30 serial communication controller */ |
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# define HAVE_NESCC 0 /* No Enhanced Serial Communication Controllers */ |
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# undef HAVE_16550 /* No 16550 MIMIC */ |
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# define HAVE_NIOLINES 16 /* Sixteen (16) I/O lines */ |
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# define HAVE_NPAR8 0 /* No 8-bit parallel ports */ |
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# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ |
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/* Z80182 |
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* |
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* The Z80182 and Z8L182 MPUs are smart peripheral controller ICs for modems, fax, |
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* voice messaging, and other communications applications. It uses the Z80180 |
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* microprocessor linked with two channels of the industry-standard Z85230 ESCC, |
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* 24 bits of parallel I/O, and a 16550 MIMIC for direct connection to the IBM PC, |
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* XT, or AT bus |
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* |
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* Z80182 Features |
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* |
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* Enhanced Z80 CPU |
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* 1 MB MMU |
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* 2 DMAs |
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* 2 UARTs (up to 512 Kbps) |
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* Two 16-Bit Timers |
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* Clock Serial I/O |
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* Power-Down Mode |
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* Divide-by-One/Divide-by-Two/Multiply-by-Two Clock Options |
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* Enhanced Serial Communication Controller (ESCC) (2 Channels) with 32-Bit CRC |
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* 16550 MIMIC |
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* 24 Parallel I/O |
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* 3.3 V and 5 V Version |
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*/ |
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#elif defined(CONFIG_ARCH_CHIP_Z8018233FSG) || /* 100-pin QFP */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018220AEG) || /* 100-pin LQFP 20MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018216FSG) || /* 100-pin QFP 16MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018216ASG) || /* 100-pin LQFP */ \ |
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defined(CONFIG_ARCH_CHIP_Z8018233ASG) /* 100-pin LQFP 33MHz 5V */ |
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */ |
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# undef HAVE_Z8X180 /* Z8x180 registers */ |
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# undef HAVE_Z8X181 /* Z8x181 registers */ |
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# define HAVE_Z8X182 1 /* Z8x182 registers */ |
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# define HAVE ROM 0 /* No on-chip ROM */ |
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */ |
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# undef HAVE_WDT /* No Watchdog timer */ |
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# define HAVE_NTIMERS16 2 /* Two (2) 16-bit timers ? */ |
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# define HAVE_NCTCS 0 /* No Counter/Timers (CTCs) */ |
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# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
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# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
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# define HAVE_NSCC 0 /* No Z85C30 serial communication controller */ |
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# define HAVE_NESCC 2 /* Two (2) Z85230 Enhanced Serial Communication Controllers */ |
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# define HAVE_16550 1 /* Have 16550 MIMIC */ |
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# define HAVE_NIOLINES 0 /* No I/O lines */ |
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# define HAVE_NPAR8 3 /* Three (3) 8-bit parallel ports (24-bit) */ |
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# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ |
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/* Z80195 |
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* |
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* The Z80195 MPU is a smart peripheral controller device designed for general data |
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* communications applications, and architected specifically to accommodate all |
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* input and output (I/O) requirements for serial and parallel connectivity. |
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* Combining a high-performance CPU core with a variety of system and I/O |
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* resources, the Z80195 is useful in a broad range of applications. |
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* |
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* Z80195 Features |
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* |
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* Enhanced Z80 CPU |
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* 1 MB MMU |
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* 2 DMAs |
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* 2 UARTs (up to 512 Kbps) |
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* Two 16-Bit Timers |
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* 4 Counter/Timers |
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* Clock Serial I/O |
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* Power-Down Mode |
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* 32 K ROM (185) |
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* 1 Ch ESCC |
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* IEEE 1284 Bi-Directional Centronics Parallel Port |
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* 7 or 24 Bits of I/O |
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*/ |
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#elif defined(CONFIG_ARCH_CHIP_Z8019520FSG) || /* 100-pin QFP 20MHz 5V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8019533FSG) /* 100-pin QFP 33MHz 5V */ |
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# undef HAVE_Z8S180 /* No Z8S180 (5V) or Z8L180 (3.3V) core */ |
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# undef HAVE ROM 0 /* No 32KB on-chip ROM (z80185 only) */ |
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */ |
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# defube HAVE_WDT 1 /* Have Watchdog timer */ |
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# define HAVE_NTIMERS16 2 /* Two (2) 16-bit counter/timers */ |
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# define HAVE_NCTCS 4 /* Four (4) Counter/Timers (CTCs) */ |
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# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
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# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
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# define HAVE_NSCC 0 /* No Z85C30 serial communication controller */ |
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# define HAVE_NESCC 1 /* One (1) Enhanced Serial Communication Controllers (EMSCC) */ |
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# undef HAVE_16550 /* No 16550 MIMIC */ |
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# define HAVE_NIOLINES 0 /* No I/O lines */ |
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# define HAVE_NPAR8 2 /* Two (s) 8-bit parallel ports (or 17-bit IEEE 1284) */ |
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# define HAVE_IEEE1284 1 /* Have bidirectional centronics interface (IEEE 1284) */ |
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/* Z8L180 |
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* |
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* The enhanced Z8S180/Z8L180 significantly improves on previous Z80180 models, |
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* while still providing full backward compatibility with existing ZiLOG Z80 |
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* devices. The Z8S180/Z8L180 now offers faster execution speeds, power-saving |
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* modes, and EMI noise reduction. |
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* |
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* Z8L180 Features |
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* |
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* Enhanced Z80 CPU |
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* 1 MB MMU |
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* 2 DMAs* |
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* 2 UARTs* (up to 512 Kbps) |
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* Two 16-Bit Timers |
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* Clock Serial I/O |
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* On-Chip Oscillator |
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* Power-Down Mode* |
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* Divide-by-One/Divide-by-Two/Multiply-by-Two Clock Options* |
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* Programmable Driver Strength for EMI Tuning |
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* |
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* * Enhanced on the Z8S180 and Z8L180 MPUs. |
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*/ |
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#elif defined(CONFIG_ARCH_CHIP_Z8L18020VSG) || /* 68-pinn PLCC */ \ |
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defined(CONFIG_ARCH_CHIP_Z8L18020FSG) || /* 80-pin GFP 20MHz 3.3V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8L18020PSG) |
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# define HAVE_Z8S180 1 /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */ |
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# define HAVE_Z8X180 1 /* Z8x180 registers */ |
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# undef HAVE_Z8X181 /* Z8x181 registers */ |
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# undef HAVE_Z8X182 /* Z8x182 registers */ |
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# define HAVE ROM 0 /* No on-chip ROM */ |
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */ |
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# undef HAVE_WDT /* No Watchdog timer */ |
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# define HAVE_NTIMERS16 2 /* Two (2) 16-bit timers */ |
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# define HAVE_NCTCS 0 /* No Counter/Timers (CTCs) */ |
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# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
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# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
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# define HAVE_NSCC 0 /* No serial communication controller */ |
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# define HAVE_NESCC 0 /* No Enhanced Serial Communication Controllers */ |
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# undef HAVE_16550 /* No 16550 MIMIC */ |
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# define HAVE_NIOLINES 0 /* No I/O lines */ |
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# define HAVE_NPAR8 0 /* No 8-bit parallel ports */ |
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# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ |
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/* Z8L182 |
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* |
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* The Z80182/Z8L182 is a smart peripheral controller IC for modem (in particular |
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* V. Fast applications), fax, voice messaging and other communications |
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* applications. It uses the Z80180 microprocessor (Z8S180 MPU core) linked with |
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* two channels of the industry standard Z85230 ESCC (Enhanced Serial |
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|
* Communications Controller), 24 bits of parallel I/O, and a 16550 MIMIC for |
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|
* direct connection to the IBM PC, XT, AT bus. |
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* |
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* Z8L182 Features |
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* |
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* Enhanced Z80 CPU |
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* 1 MB MMU |
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* 2 DMAs |
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* 2 UARTs (up to 512 Kbps) |
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* Two 16-Bit Timers |
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* Clock Serial I/O |
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* Power-Down Mode |
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* Divide-by-One/Divide-by-Two/Multiply-by-Two Clock Options |
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* ESCC (2 Channels) with 32-Bit CRC |
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* 16550 MIMIC |
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* 24 Parallel I/O |
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* 3.3 V and 5 V Version |
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*/ |
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#elif defined(CONFIG_ARCH_CHIP_Z8L18220ASG) || /* 100-pin LQFP */ \ |
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defined(CONFIG_ARCH_CHIP_Z8L18220FSG) || /* 100-pin QFP 20MHz 3.3V */ \ |
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defined(CONFIG_ARCH_CHIP_Z8L18220AEG) |
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# define HAVE_Z8S180 1 /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */ |
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# undef HAVE_Z8X180 /* Z8x180 registers */ |
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# undef HAVE_Z8X181 /* Z8x181 registers */ |
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# define HAVE_Z8X182 1 /* Z8x182 registers */ |
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# define HAVE ROM 0 /* No on-chip ROM */ |
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */ |
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|
# undef HAVE_WDT /* No Watchdog timer */ |
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# define HAVE_NTIMERS16 2 /* Two (2) 16-bit timers ? */ |
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# define HAVE_NCTCS 0 /* No Counter/Timers (CTCs) */ |
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# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
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# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
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# define HAVE_NSCC 0 /* No Z85C30 serial communication controller */ |
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# define HAVE_NESCC 2 /* Two (2) Z85230 Enhanced Serial Communication Controllers */ |
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# define HAVE_16550 1 /* Have 16550 MIMIC */ |
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# define HAVE_NIOLINES 0 /* No I/O lines */ |
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# define HAVE_NPAR8 3 /* Three (3) 8-bit parallel ports (24-bit) */ |
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# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ |
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|
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/* Z8SL180 |
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* |
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* The enhanced Z8S180/Z8L180 significantly improves on previous Z80180 models, |
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* while still providing full backward compatibility with existing ZiLOG Z80 |
|
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* devices. The Z8S180/Z8L180 now offers faster execution speeds, power-saving |
|
|
* modes, and EMI noise reduction.This enhanced Z180 design also incorporates |
|
|
* additional feature enhancements to the ASCIs, DMAs, and STANDBY mode power |
|
|
* consumption. With the addition of ESCC-like Baud Rate Generators (BRGs), the |
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|
* two ASCIs offer the flexibility and capability to transfer data |
|
|
* asynchronously at rates of up to 512 Kbps. |
|
|
* |
|
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* Z8S180 Features |
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* |
|
|
* External Memory - 1 |
|
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* Voltage Range - 5.0V |
|
|
* Communications Controller - CSIO, UART |
|
|
* Other Features - 1MB MMU, 2xDMA<EFBFBD>s, 2xUARTs |
|
|
* Speed (MHz) - 20, 10, 33 |
|
|
* Core / CPU Used - Z180 |
|
|
* Pin Count - 64, 68, 80 |
|
|
* Timers - 2 |
|
|
* I/O - Clock Serial |
|
|
* Package - DIP, PLCC, QFP |
|
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*/ |
|
|
|
|
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#elif defined(CONFIG_ARCH_CHIP_Z8S18020VSG) || /* 68-pin PLCC */ \ |
|
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defined(CONFIG_ARCH_CHIP_Z8S18020VSG1960) || /* 68-pin PLCC */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18033VSG) || /* 68-pin PLCC */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18010FSG) || /* 80-pin QFP */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18010VEG) || /* 68-pin PLCC */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18020VEG) || /* 68-pin PLCC */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18010VSG) || /* 68-pin PLCC */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18020PSG) || /* 64-pin DIP 10Mhz 5V */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18033FSG) || /* 80-pin QFP 33MHz 5V */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18033FEG) || /* 80-pin QFP 33MHz 5V */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18020FSG) || /* 80-pin QFP 20MHz 5V */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18033VEG) || /* 68-pin PLCC 33MHz 5V */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18010PSG) || /* 64-pin DIP 10MHz 5V */ \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18020FEG) || \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18010PEG) || \ |
|
|
defined(CONFIG_ARCH_CHIP_Z8S18010FEG) |
|
|
|
|
|
# define HAVE_Z8S180 1 /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */ |
|
|
# define HAVE_Z8X180 1 /* Z8x180 registers */ |
|
|
# undef HAVE_Z8X181 /* Z8x181 registers */ |
|
|
# undef HAVE_Z8X182 /* Z8x182 registers */ |
|
|
# define HAVE ROM 0 /* No on-chip ROM */ |
|
|
# define HAVE_SERIALIO 1 /* Have clocked serial I/O */ |
|
|
# undef HAVE_WDT /* No Watchdog timer */ |
|
|
# define HAVE_NTIMERS16 2 /* Two (2) 16-bit timers */ |
|
|
# define HAVE_NCTCS 0 /* No Counter/Timers (CTCs) */ |
|
|
# define HAVE_NDMA 2 /* Two (2) DMA channels */ |
|
|
# define HAVE_NUARTS 2 /* Two (2) UARTs (up to 512 Kbps) */ |
|
|
# define HAVE_NSCC 0 /* No serial communication controller */ |
|
|
# define HAVE_NESCC 0 /* No Enhanced Serial Communication Controllers */ |
|
|
# undef HAVE_16550 /* No 16550 MIMIC */ |
|
|
# define HAVE_NIOLINES 0 /* No I/O lines */ |
|
|
# define HAVE_NPAR8 0 /* No 8-bit parallel ports */ |
|
|
# undef HAVE_IEEE1284 /* No bidirectional centronics interface (IEEE 1284) */ |
|
|
|
|
|
#else |
|
|
# error "Unrecognized/undefined Z180 chip" |
|
|
#endif |
|
|
|
|
|
/**************************************************************************** |
|
|
* Public Types |
|
|
****************************************************************************/ |
|
|
|
|
|
/**************************************************************************** |
|
|
* Inline functions |
|
|
****************************************************************************/ |
|
|
|
|
|
/**************************************************************************** |
|
|
* Public Variables |
|
|
****************************************************************************/ |
|
|
|
|
|
/**************************************************************************** |
|
|
* Public Function Prototypes |
|
|
****************************************************************************/ |
|
|
|
|
|
#endif /* __ARCH_Z80_INCLUDE_Z180_CHIP_H */
|
|
|
|
