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342 lines
13 KiB
342 lines
13 KiB
/************************************************************************************ |
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* board.h |
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* |
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* Copyright (C) 2016-2018 Gregory Nutt. All rights reserved. |
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* Authors: David Sidrane <david_s5@nscdg.com> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#pragma once |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include "stm32_rcc.h" |
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/************************************************************************************ |
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* Pre-processor Definitions |
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************************************************************************************/ |
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/* Clocking *************************************************************************/ |
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/* The KakuteF7 board provides the following clock sources: |
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* |
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* 8 MHz crystal for HSE |
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* |
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* So we have these clock source available within the STM32 |
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* |
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* HSI: 16 MHz RC factory-trimmed |
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* HSE: 8 MHz crystal for HSE |
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*/ |
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#define STM32_BOARD_XTAL 8000000ul |
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#define STM32_HSI_FREQUENCY 16000000ul |
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#define STM32_LSI_FREQUENCY 32000 |
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL |
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#define STM32_LSE_FREQUENCY 0 |
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/* Main PLL Configuration. |
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* |
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* PLL source is HSE = 8,000,000 |
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* |
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN |
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* Subject to: |
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* |
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* 2 <= PLLM <= 63 |
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* 192 <= PLLN <= 432 |
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* 192 MHz <= PLL_VCO <= 432MHz |
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* |
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* SYSCLK = PLL_VCO / PLLP |
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* Subject to |
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* |
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* PLLP = {2, 4, 6, 8} |
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* SYSCLK <= 216 MHz |
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* |
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* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ |
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* Subject to |
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* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC |
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* and the random number generator need a frequency lower than or equal |
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* to 48 MHz to work correctly. |
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* |
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* 2 <= PLLQ <= 15 |
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*/ |
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/* Highest SYSCLK with USB OTG FS clock = 48 MHz |
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* |
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* PLL_VCO = (8,000,000 / 8) * 432 = 432 MHz |
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* SYSCLK = 432 MHz / 2 = 216 MHz |
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* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz |
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*/ |
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) |
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432) |
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 |
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9) |
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 432) |
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) |
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9) |
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/* Configure factors for PLLSAI clock */ |
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#define CONFIG_STM32F7_PLLSAI 1 |
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(384) |
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) |
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) |
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) |
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/* Configure Dedicated Clock Configuration Register */ |
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#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) |
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1) |
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0) |
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#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0) |
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#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0) |
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#define STM32_RCC_DCKCFGR1_TIMPRESRC 0 |
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#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 |
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#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 |
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/* Configure factors for PLLI2S clock */ |
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#define CONFIG_STM32F7_PLLI2S 1 |
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(384) |
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) |
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) |
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) |
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/* Configure Dedicated Clock Configuration Register 2 */ |
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#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB |
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#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB |
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#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB |
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#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB |
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#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB |
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#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB |
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#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB |
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#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI |
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#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI |
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#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI |
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#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI |
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#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB |
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#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI |
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#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL |
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#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ |
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#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ |
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#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY |
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/* Several prescalers allow the configuration of the two AHB buses, the |
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* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum |
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* frequency of the two AHB buses is 216 MHz while the maximum frequency of |
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* the high-speed APB domains is 108 MHz. The maximum allowed frequency of |
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* the low-speed APB domain is 54 MHz. |
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*/ |
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/* AHB clock (HCLK) is SYSCLK (216 MHz) */ |
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ |
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY |
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ |
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */ |
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ |
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) |
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/* Timers driven from APB1 will be twice PCLK1 */ |
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ |
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ |
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* Timers driven from APB2 will be twice PCLK2 */ |
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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/* FLASH wait states |
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* |
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* --------- ---------- ----------- |
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* VDD MAX SYSCLK WAIT STATES |
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* --------- ---------- ----------- |
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* 1.7-2.1 V 180 MHz 8 |
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* 2.1-2.4 V 216 MHz 9 |
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* 2.4-2.7 V 216 MHz 8 |
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* 2.7-3.6 V 216 MHz 7 |
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* --------- ---------- ----------- |
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*/ |
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#define BOARD_FLASH_WAITSTATES 7 |
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/* LED definitions ******************************************************************/ |
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/* LED index values for use with board_userled() */ |
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#define BOARD_LED1 0 |
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#define BOARD_NLEDS 1 |
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#define BOARD_LED_BLUE BOARD_LED1 |
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/* LED bits for use with board_userled_all() */ |
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#define BOARD_LED1_BIT (1 << BOARD_LED1) |
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in |
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* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related |
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* events as follows: |
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* |
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* |
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* SYMBOL Meaning LED state |
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* Red Green Blue |
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* ---------------------- -------------------------- ------ ------ ----*/ |
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ |
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ |
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ |
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ |
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ |
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ |
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ |
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ |
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ |
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/* Alternate function pin selections (see stm32f74xx75xx_pinmap.h) ******************************/ |
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */ |
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#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */ |
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#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */ |
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */ |
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#define GPIO_USART3_RX GPIO_USART3_RX_1 /* PB11 */ |
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#define GPIO_USART3_TX GPIO_USART3_TX_1 /* PB10 */ |
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#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */ |
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#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */ |
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */ |
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#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */ |
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#define GPIO_UART7_RX GPIO_UART7_RX_1 /* PE7 */ |
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#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE8 */ |
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/* SPI |
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* SPI1 SD Card |
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* SPI2 is OSD AT7456E |
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* SPI4 is IMU |
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*/ |
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */ |
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */ |
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */ |
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */ |
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */ |
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3 /* PB13 */ |
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#define GPIO_SPI4_MISO GPIO_SPI4_MISO_1 /* PE5 */ |
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#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */ |
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#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 /* PE2 */ |
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/* I2C |
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*/ |
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 /* PB6 */ |
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 /* PB7 */ |
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#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6) |
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#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7) |
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/* USB |
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* |
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* OTG_FS_DM PA11 |
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* OTG_FS_DP PA12 |
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* VBUS PA8 |
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*/ |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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#undef EXTERN |
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#if defined(__cplusplus) |
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#define EXTERN extern "C" |
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extern "C" |
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{ |
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#else |
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#define EXTERN extern |
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#endif |
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/************************************************************************************ |
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* Public Function Prototypes |
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************************************************************************************/ |
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/************************************************************************************ |
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* Name: stm32_boardinitialize |
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* |
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* Description: |
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* All STM32 architectures must provide the following entry point. This entry point |
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* is called early in the initialization -- after all memory has been configured |
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* and mapped but before any devices have been initialized. |
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* |
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************************************************************************************/ |
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void stm32_boardinitialize(void); |
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#undef EXTERN |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif /* __ASSEMBLY__ */
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