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398 lines
18 KiB
398 lines
18 KiB
/************************************************************************************ |
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* nuttx-configs/nxp_fmurt1062-v1/include/board.h |
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* |
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* Copyright (C) 2018 Gregory Nutt. All rights reserved. |
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* Authors: Gregory Nutt <gnutt@nuttx.org> |
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* David Sidrane <david_s5@nscdg.com> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#ifndef __NUTTX_CONFIG_NXP_FMURT1062_V1_INCLUDE_BOARD_H |
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#define __NUTTX_CONFIG_NXP_FMURT1062_V1_INCLUDE_BOARD_H |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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/************************************************************************************ |
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* Pre-processor Definitions |
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************************************************************************************/ |
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/* Clocking *************************************************************************/ |
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/* Set VDD_SOC to 1.3V */ |
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#define IMXRT_VDD_SOC (0x14) |
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/* Set Arm PLL (PLL1) to fOut = (24Mhz * ARM_PLL_DIV_SELECT/2) / ARM_PODF_DIVISOR |
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* 576Mhz = (24Mhz * ARM_PLL_DIV_SELECT/2) / ARM_PODF_DIVISOR |
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* ARM_PLL_DIV_SELECT = 96 |
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* ARM_PODF_DIVISOR = 2 |
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* 576Mhz = (24Mhz * 96/2) / 2 |
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* |
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* AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER |
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* 1Hz to 600 Mhz = 576Mhz / IMXRT_ARM_CLOCK_DIVIDER |
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* IMXRT_ARM_CLOCK_DIVIDER = 1 |
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* 576Mhz = 576Mhz / 1 |
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* |
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* PRE_PERIPH_CLK_SEL = PRE_PERIPH_CLK_SEL_PLL1 |
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* PERIPH_CLK_SEL = 1 (0 select PERIPH_CLK2_PODF, 1 select PRE_PERIPH_CLK_SEL_PLL1) |
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* PERIPH_CLK = 576Mhz |
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* |
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* IPG_CLOCK_ROOT = AHB_CLOCK_ROOT / IMXRT_IPG_PODF_DIVIDER |
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* IMXRT_IPG_PODF_DIVIDER = 4 |
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* 144Mhz = 576Mhz / 4 |
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* |
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* PRECLK_CLOCK_ROOT = IPG_CLOCK_ROOT / IMXRT_PERCLK_PODF_DIVIDER |
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* IMXRT_PERCLK_PODF_DIVIDER = 1 |
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* 16Mhz = 144Mhz / 9 |
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* |
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* SEMC_CLK_ROOT = 576Mhz / IMXRT_SEMC_PODF_DIVIDER (labeled AIX_PODF in 18.2) |
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* IMXRT_SEMC_PODF_DIVIDER = 8 |
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* 72Mhz = 576Mhz / 8 |
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* |
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* Set Sys PLL (PLL2) to fOut = (24Mhz * (20+(2*(DIV_SELECT))) |
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* 528Mhz = (24Mhz * (20+(2*(1))) |
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* |
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* Set USB1 PLL (PLL3) to fOut = (24Mhz * 20) |
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* 480Mhz = (24Mhz * 20) |
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* |
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* Set LPSPI PLL3 PFD0 to fOut = (480Mhz / 12 * 18) |
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* 720Mhz = (480Mhz / 12 * 18) |
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* 90Mhz = (720Mhz / LSPI_PODF_DIVIDER) |
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* |
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* Set LPI2C PLL3 / 8 to fOut = (480Mhz / 8) |
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* 60Mhz = (480Mhz / 8) |
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* 12Mhz = (60Mhz / LSPI_PODF_DIVIDER) |
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* |
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* Set USDHC1 PLL2 PFD2 to fOut = (528Mhz / 24 * 18) |
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* 396Mhz = (528Mhz / 24 * 18) |
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* 198Mhz = (396Mhz / IMXRT_USDHC1_PODF_DIVIDER) |
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*/ |
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#define BOARD_XTAL_FREQUENCY 24000000 |
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#define IMXRT_PRE_PERIPH_CLK_SEL CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1 |
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#define IMXRT_PERIPH_CLK_SEL CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH |
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#define IMXRT_ARM_PLL_DIV_SELECT 96 |
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#define IMXRT_ARM_PODF_DIVIDER 2 |
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#define IMXRT_AHB_PODF_DIVIDER 1 |
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#define IMXRT_IPG_PODF_DIVIDER 4 |
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#define IMXRT_PERCLK_CLK_SEL CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT |
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#define IMXRT_PERCLK_PODF_DIVIDER 9 |
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#define IMXRT_SEMC_PODF_DIVIDER 8 |
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#define IMXRT_LPSPI_CLK_SELECT CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 |
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#define IMXRT_LSPI_PODF_DIVIDER 8 |
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#define IMXRT_LPI2C_CLK_SELECT CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M |
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#define IMXRT_LSI2C_PODF_DIVIDER 5 |
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#define IMXRT_USDHC1_CLK_SELECT CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 |
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#define IMXRT_USDHC1_PODF_DIVIDER 2 |
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#define IMXRT_SYS_PLL_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22 |
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#define IMXRT_USB1_PLL_DIV_SELECT CCM_ANALOG_PLL_USB1_DIV_SELECT_20 |
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#define BOARD_CPU_FREQUENCY \ |
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(BOARD_XTAL_FREQUENCY * (IMXRT_ARM_PLL_DIV_SELECT / 2)) / IMXRT_ARM_PODF_DIVIDER |
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#define BOARD_GPT_FREQUENCY \ |
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(BOARD_CPU_FREQUENCY / IMXRT_IPG_PODF_DIVIDER) / IMXRT_PERCLK_PODF_DIVIDER |
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/* Define this to enable tracing */ |
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#if CONFIG_USE_TRACE |
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# define IMXRT_TRACE_PODF_DIVIDER 1 |
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# define IMXRT_TRACE_CLK_SELECT CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 |
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#endif |
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/* SDIO *****************************************************************************/ |
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/* Pin drive characteristics */ |
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#define USDHC1_DATAX_IOMUX (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER) |
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#define USDHC1_CMD_IOMUX (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER) |
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#define USDHC1_CLK_IOMUX (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_SPEED_MAX) |
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#define USDHC1_CD_IOMUX (IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER) |
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#define PIN_USDHC1_D0 (GPIO_USDHC1_DATA0_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_02 */ |
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#define PIN_USDHC1_D1 (GPIO_USDHC1_DATA1_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_03 */ |
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#define PIN_USDHC1_D2 (GPIO_USDHC1_DATA2_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_04 */ |
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#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_05 */ |
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#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | USDHC1_CLK_IOMUX) /* GPIO_SD_B0_01 */ |
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#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | USDHC1_CMD_IOMUX) /* GPIO_SD_B0_00 */ |
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#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | USDHC1_CD_IOMUX) /* GPIO_B1_12 */ |
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/* Ideal 400Khz for initial inquiry. |
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* Given input clock 198 Mhz. |
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* 386.71875 KHz = 198 Mhz / (256 * 2) |
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*/ |
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#define BOARD_USDHC_IDMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV256 |
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#define BOARD_USDHC_IDMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(2) |
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/* Ideal 25 Mhz for other modes |
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* Given input clock 198 Mhz. |
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* 24.75 MHz = 198 Mhz / (8 * 1) |
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*/ |
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#define BOARD_USDHC_MMCMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 |
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#define BOARD_USDHC_MMCMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) |
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#define BOARD_USDHC_SD1MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 |
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#define BOARD_USDHC_SD1MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) |
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#define BOARD_USDHC_SD4MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 |
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#define BOARD_USDHC_SD4MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) |
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/* LED definitions ******************************************************************/ |
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/* The nxp fmutr1062 board has numerous LEDs but only three, LED_GREEN a Green LED, |
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* LED_BLUE a Blue LED and LED_RED a Red LED, that can be controlled by software. |
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* |
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way. |
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* The following definitions are used to access individual LEDs. |
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*/ |
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/* LED index values for use with board_userled() */ |
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#define BOARD_LED1 0 |
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#define BOARD_LED2 1 |
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#define BOARD_LED3 2 |
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#define BOARD_NLEDS 3 |
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#define BOARD_LED_RED BOARD_LED1 |
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#define BOARD_LED_GREEN BOARD_LED2 |
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#define BOARD_LED_BLUE BOARD_LED3 |
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/* LED bits for use with board_userled_all() */ |
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#define BOARD_LED1_BIT (1 << BOARD_LED1) |
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#define BOARD_LED2_BIT (1 << BOARD_LED2) |
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#define BOARD_LED3_BIT (1 << BOARD_LED3) |
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in |
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* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related |
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* events as follows: |
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* |
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* |
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* SYMBOL Meaning LED state |
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* Red Green Blue |
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* ---------------------- -------------------------- ------ ------ ----*/ |
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ |
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ |
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ |
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ |
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ |
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ |
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ |
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ |
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ |
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/* Thus if the Green LED is statically on, NuttX has successfully booted and |
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* is, apparently, running normally. If the Red LED is flashing at |
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* approximately 2Hz, then a fatal error has been detected and the system |
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* has halted. |
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*/ |
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/* PIO Disambiguation ***************************************************************/ |
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/* LPUARTs |
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*/ |
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#define LPUART_IOMUX (IOMUX_PULL_UP_22K | IOMUX_DRIVE_40OHM | IOMUX_SLEW_SLOW | IOMUX_SPEED_LOW | IOMUX_SCHMITT_TRIGGER) |
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/* GPS 1 */ |
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#define GPIO_LPUART2_RX (GPIO_LPUART2_RX_1 | LPUART_IOMUX) /* EVK J22-8 */ /* GPIO_AD_B1_03 */ |
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#define GPIO_LPUART2_TX (GPIO_LPUART2_TX_1 | LPUART_IOMUX) /* EVK J22-7 */ /* GPIO_AD_B1_02 */ |
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/* N.B. Rev B schematic did not change the names of the nets. Just the silk screen renamed the ports |
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* Such that Telem 2 had the real HW HS signals. The imx driver to dated does not support GOIO controlled |
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* HS lines |
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*/ |
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/* Telem 1 */ |
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#define HS_INPUT_IOMUX (IOMUX_CMOS_INPUT | IOMUX_SLEW_SLOW | IOMUX_DRIVE_HIZ | IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_47K) |
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#define HS_OUTPUT_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM | IOMUX_SPEED_MEDIUM | IOMUX_PULL_KEEP) |
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#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_3 | LPUART_IOMUX) /* GPIO_B0_09 */ |
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_3 | LPUART_IOMUX) /* GPIO_B0_08 */ |
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#define GPIO_LPUART3_CTS (GPIO_PORT3 | GPIO_PIN4 | GPIO_INPUT | HS_INPUT_IOMUX) /* GPIO_SD_B1_04 GPIO3_IO04 (GPIO only, no HW Flow control) */ |
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#define GPIO_LPUART3_RTS (GPIO_PORT4 | GPIO_PIN24 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | HS_OUTPUT_IOMUX) /* GPIO_EMC_24 GPIO4_IO24 (GPIO only, no HW Flow control) */ |
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/* Telem 2 */ |
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#define GPIO_LPUART4_RX (GPIO_LPUART4_RX_2 | LPUART_IOMUX) /* GPIO_EMC_20 */ |
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#define GPIO_LPUART4_TX (GPIO_LPUART4_TX_2 | LPUART_IOMUX) /* GPIO_EMC_19 */ |
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#define GPIO_LPUART4_CTS (GPIO_LPUART4_CTS_1 | LPUART_IOMUX) /* GPIO_EMC_17 */ |
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#define GPIO_LPUART4_RTS (GPIO_LPUART4_RTS_1 | LPUART_IOMUX) /* GPIO_EMC_18 */ |
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/* GPS2 */ |
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#define GPIO_LPUART5_RX (GPIO_LPUART5_RX_1 | LPUART_IOMUX) /* GPIO_B1_13 */ |
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#define GPIO_LPUART5_TX (GPIO_LPUART5_TX_2 | LPUART_IOMUX) /* GPIO_EMC_23 */ |
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/* RC INPUT single wire mode on TX, RX is not used */ |
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#define GPIO_LPUART6_RX (GPIO_LPUART6_RX_2 | LPUART_IOMUX) /* GPIO_EMC_26 */ |
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#define GPIO_LPUART6_TX (GPIO_LPUART6_TX_2 | LPUART_IOMUX) /* GPIO_EMC_25 */ |
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#define GPIO_LPUART7_RX (GPIO_LPUART7_RX_1 | LPUART_IOMUX) /* GPIO_EMC_32 */ |
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#define GPIO_LPUART7_TX (GPIO_LPUART7_TX_1 | LPUART_IOMUX) /* GPIO_EMC_31 */ |
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#define GPIO_LPUART8_RX (GPIO_LPUART8_RX_2 | LPUART_IOMUX) /* GPIO_EMC_39 */ |
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#define GPIO_LPUART8_TX (GPIO_LPUART8_TX_2 | LPUART_IOMUX) /* GPIO_EMC_38 */ |
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/* CAN |
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* |
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* CAN1 is routed to transceiver. |
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* CAN2 is routed to transceiver. |
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* CAN3 is routed to transceiver. |
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*/ |
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#define FLEXCAN_IOMUX (IOMUX_PULL_UP_100K | IOMUX_DRIVE_40OHM | IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM) |
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#define GPIO_FLEXCAN1_RX (GPIO_FLEXCAN1_RX_2 | FLEXCAN_IOMUX) /* GPIO_B0_03 */ |
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#define GPIO_FLEXCAN1_TX (GPIO_FLEXCAN1_TX_4 | FLEXCAN_IOMUX) /* GPIO_SD_B1_02 */ |
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#define GPIO_FLEXCAN2_RX (GPIO_FLEXCAN2_RX_1 | FLEXCAN_IOMUX) /* GPIO_AD_B0_03 */ |
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#define GPIO_FLEXCAN2_TX (GPIO_FLEXCAN2_TX_1 | FLEXCAN_IOMUX) /* GPIO_AD_B0_02 */ |
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#define GPIO_FLEXCAN3_RX (GPIO_FLEXCAN3_RX_1 | FLEXCAN_IOMUX) /* GPIO_AD_B0_11 */ |
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#define GPIO_FLEXCAN3_TX (GPIO_FLEXCAN3_TX_3 | FLEXCAN_IOMUX) /* GPIO_EMC_36 */ |
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/* LPSPI */ |
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#define LPSPI_IOMUX (IOMUX_PULL_UP_100K | IOMUX_DRIVE_33OHM | IOMUX_SLEW_FAST | IOMUX_SPEED_MAX) |
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#define GPIO_LPSPI1_SCK (GPIO_LPSPI1_SCK_1 | LPSPI_IOMUX) /* GPIO_EMC_27 */ |
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#define GPIO_LPSPI1_MISO (GPIO_LPSPI1_SDI_1 | LPSPI_IOMUX) /* GPIO_EMC_29 */ |
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#define GPIO_LPSPI1_MOSI (GPIO_LPSPI1_SDO_1 | LPSPI_IOMUX) /* GPIO_EMC_28 */ |
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#define GPIO_LPSPI2_SCK (GPIO_LPSPI2_SCK_1 | LPSPI_IOMUX) /* GPIO_EMC_00 */ |
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#define GPIO_LPSPI2_MISO (GPIO_LPSPI2_SDI_1 | LPSPI_IOMUX) /* GPIO_EMC_03 */ |
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#define GPIO_LPSPI2_MOSI (GPIO_LPSPI2_SDO_1 | LPSPI_IOMUX) /* GPIO_EMC_02 */ |
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#define GPIO_LPSPI3_SCK (GPIO_LPSPI3_SCK_1 | LPSPI_IOMUX) /* GPIO_AD_B1_15 */ |
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#define GPIO_LPSPI3_MISO (GPIO_LPSPI3_SDI_1 | LPSPI_IOMUX) /* GPIO_AD_B1_13 */ |
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#define GPIO_LPSPI3_MOSI (GPIO_LPSPI3_SDO_1 | LPSPI_IOMUX) /* GPIO_AD_B1_14 */ |
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#define GPIO_LPSPI4_SCK (GPIO_LPSPI4_SCK_1 | LPSPI_IOMUX) /* GPIO_B1_07 */ |
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#define GPIO_LPSPI4_MISO (GPIO_LPSPI4_SDI_1 | LPSPI_IOMUX) /* GPIO_B1_05 */ |
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#define GPIO_LPSPI4_MOSI (GPIO_LPSPI4_SDO_2 | LPSPI_IOMUX) /* GPIO_B0_02 */ |
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/* LPI2Cs */ |
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#define LPI2C_IOMUX (IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM | IOMUX_OPENDRAIN | GPIO_SION_ENABLE) |
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#define LPI2C_IO_IOMUX (IOMUX_SPEED_MAX | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM | IOMUX_OPENDRAIN | IOMUX_PULL_NONE) |
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#define GPIO_LPI2C1_SDA (GPIO_LPI2C1_SDA_2 | LPI2C_IOMUX) /* EVK J24-9 R276 */ /* GPIO_AD_B1_01 */ |
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#define GPIO_LPI2C1_SCL (GPIO_LPI2C1_SCL_2 | LPI2C_IOMUX) /* EVK J24-10 R277 */ /* GPIO_AD_B1_00 */ |
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#define GPIO_LPI2C1_SDA_RESET (GPIO_PORT1 | GPIO_PIN17 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_AD_B1_01 GPIO1_IO17 */ |
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#define GPIO_LPI2C1_SCL_RESET (GPIO_PORT1 | GPIO_PIN16 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_AD_B1_00 GPIO1_IO16 */ |
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#define GPIO_LPI2C2_SDA (GPIO_LPI2C2_SDA_1 | LPI2C_IOMUX) /* EVK J8-A25 */ /* GPIO_B0_05 */ |
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#define GPIO_LPI2C2_SCL (GPIO_LPI2C2_SCL_1 | LPI2C_IOMUX) /* EVK J8-A24 */ /* GPIO_B0_04 */ |
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#define GPIO_LPI2C2_SDA_RESET (GPIO_PORT2 | GPIO_PIN5 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_B0_05 GPIO2_IO5 */ |
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#define GPIO_LPI2C2_SCL_RESET (GPIO_PORT2 | GPIO_PIN4 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_B0_04 GPIO2_IO4 */ |
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#define GPIO_LPI2C3_SDA (GPIO_LPI2C3_SDA_2 | LPI2C_IOMUX) /* GPIO_EMC_21 */ |
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#define GPIO_LPI2C3_SCL (GPIO_LPI2C3_SCL_2 | LPI2C_IOMUX) /* GPIO_EMC_22 */ |
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#define GPIO_LPI2C3_SDA_RESET (GPIO_PORT4 | GPIO_PIN21 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_EMC_21 GPIO4_IO21 */ |
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#define GPIO_LPI2C3_SCL_RESET (GPIO_PORT4 | GPIO_PIN22 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_EMC_22 GPIO4_IO22 */ |
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/* Board provides GPIO or other Hardware for signaling to timing analyzer */ |
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#if defined(CONFIG_BOARD_USE_PROBES) |
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#include <imxrt_gpio.h> |
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#include <imxrt_iomuxc.h> |
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// add -I<full path> build/nxp_fmurt1062-v1_default/NuttX/nuttx/arch/arm/src/chip \ to NuttX Makedefs.in |
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#define PROBE_IOMUX (IOMUX_SPEED_MAX | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM | IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE) |
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# define PROBE_N(n) (1<<((n)-1)) |
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# define PROBE_1 /* GPIO_B0_06 */ (GPIO_PORT2 | GPIO_PIN6 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) |
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# define PROBE_2 /* GPIO_EMC_08 */ (GPIO_PORT4 | GPIO_PIN8 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) |
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# define PROBE_3 /* GPIO_EMC_10 */ (GPIO_PORT4 | GPIO_PIN10 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) |
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# define PROBE_4 /* GPIO_AD_B0_09 */ (GPIO_PORT1 | GPIO_PIN9 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) |
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# define PROBE_5 /* GPIO_EMC_33 */ (GPIO_PORT3 | GPIO_PIN19 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) |
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# define PROBE_6 /* GPIO_EMC_30 */ (GPIO_PORT4 | GPIO_PIN30 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) |
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# define PROBE_7 /* GPIO_EMC_04 */ (GPIO_PORT4 | GPIO_PIN4 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) |
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# define PROBE_8 /* GPIO_EMC_01 */ (GPIO_PORT4 | GPIO_PIN1 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) |
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# define PROBE_INIT(mask) \ |
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do { \ |
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if ((mask)& PROBE_N(1)) { imxrt_config_gpio(PROBE_1); } \ |
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if ((mask)& PROBE_N(2)) { imxrt_config_gpio(PROBE_2); } \ |
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if ((mask)& PROBE_N(3)) { imxrt_config_gpio(PROBE_3); } \ |
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if ((mask)& PROBE_N(4)) { imxrt_config_gpio(PROBE_4); } \ |
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if ((mask)& PROBE_N(5)) { imxrt_config_gpio(PROBE_5); } \ |
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if ((mask)& PROBE_N(6)) { imxrt_config_gpio(PROBE_6); } \ |
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if ((mask)& PROBE_N(7)) { imxrt_config_gpio(PROBE_7); } \ |
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if ((mask)& PROBE_N(8)) { imxrt_config_gpio(PROBE_8); } \ |
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} while(0) |
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# define PROBE(n,s) do {imxrt_gpio_write(PROBE_##n,(s));}while(0) |
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# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true) |
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#else |
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# define PROBE_INIT(mask) |
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# define PROBE(n,s) |
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# define PROBE_MARK(n) |
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#endif |
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/************************************************************************************ |
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* Public Types |
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************************************************************************************/ |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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#undef EXTERN |
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#if defined(__cplusplus) |
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#define EXTERN extern "C" |
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extern "C" |
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{ |
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#else |
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#define EXTERN extern |
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#endif |
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/************************************************************************************ |
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* Public Functions |
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************************************************************************************/ |
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#undef EXTERN |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __NUTTX_CONFIG_NXP_FMURT1062_V1_INCLUDE_BOARD_H */
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