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226 lines
9.2 KiB
226 lines
9.2 KiB
/*********************************************************************** |
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* rinsn32.h |
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* 32-bit register module instruction definitions |
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* |
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* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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***********************************************************************/ |
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#ifndef __RINSN32_H |
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#define __RINSN32_H |
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/*********************************************************************** |
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* Included Files |
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***********************************************************************/ |
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#include <stdint.h> |
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/*********************************************************************** |
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* Pre-processor Definitions |
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***********************************************************************/ |
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/* 32-bit op-code bit definitions |
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* |
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* Machine model: |
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* |
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* SPB 32-bit Pascal stack base address |
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* SP 32-bit Pascal stack pointer |
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* LSP 32-bit level stack pointer |
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* CSB 32-bit character stack base address |
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* PC 32-bit program counter |
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* ZRO 32-bit register containing zero (like MIPS) |
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* Rn 32-bit general purpose registers |
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* |
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* Parameters passed in registers up to a limit. Parameters |
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* beyond the limit are passed on the stack. Return values |
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* are provided in these same registers. |
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* |
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* Instruction forms |
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* |
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* FORM 1: <op> <roperand1>, <operand2> |
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* FORM 2: <op> <rdest>, <operand2> |
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* FORM 3: <op> <rdest>, <roperand1>, <operand2> |
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* <rsrc>, <roperand1>, <operand2> |
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* FORM 4: <op> <pc-offset> |
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* |
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* Where |
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* <op> operation code |
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* [cc] optional conditional execution |
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* [S] optional set condition code |
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* <rdest> register holding the result |
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* <rsrc> register holding data to be stored. |
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* <roperand1> register holding the first operand |
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* <operand2> One of <roperand2> or <immediate> |
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* <roperand2> register holding the second operand |
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* <immediate> Immediate constant data (short). |
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* <pc-offset> Word offset from current PC |
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* |
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* NOTE: This instruction set is inspired by the ARM instruction |
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* set, but is intended to be a general register model. It does |
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* not exploit certain ARM-isms such as "flexible" operands, conditional |
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* execution, post-incrementing, pre-incrementing, pc-relative addressing, |
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* optional register writeback, or ldm/stm with register sets, etc. |
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*/ |
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#define FORM1(o) (((o) & 0xe0) == 0x00) |
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#define FORM1R(o) (((o) & 0xf0) == 0x00) |
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#define FORM1I(o) (((o) & 0xf0) == 0x10) |
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#define FORM1O(o) ((o) & 0x0f) |
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#define FORM2(o) (((o) & 0xe0) == 0x20) |
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#define FORM2R(o) (((o) & 0xf0) == 0x20) |
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#define FORM2I(o) (((o) & 0xf0) == 0x30) |
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#define FORM2O(o) ((o) & 0x0f) |
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#define FORM3(o) (((o) & 0x80) == 0x80) |
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#define FORM3R(o) (((o) & 0xc0) == 0x80) |
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#define FORM3I(o) (((o) & 0xc0) == 0xc0) |
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#define FORM3O(o) ((o) & 0x3f) |
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#define FORM4(o) (((o) & 0xc0) == 0x40) |
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#define FORM3O(o) ((o) & 0x3f) |
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struct rinsn_u |
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{ |
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uint8_t opcode; |
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union { |
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struct { |
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uint32_t rop1; |
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uint32_t rop2; |
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} r1; |
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struct { |
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uint32_t rop1; |
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uint32_t im2; |
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} i1; |
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struct { |
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uint32_t rdest; |
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uint32_t rop; |
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} r2; |
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struct { |
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uint32_t rdest; |
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uint32_t im; |
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} i2; |
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struct { |
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uint32_t rdest; |
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uint32_t rop1; |
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uint32_t rop2; |
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} r3; |
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struct { |
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uint32_t rdest; |
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uint32_t rop1; |
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uint32_t im2; |
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} i3; |
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struct { |
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uint32_t offset; |
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} i4; |
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} f; |
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}; |
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typedef struct rinsn_u RINSN32; |
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/* FORM 1: Comparisons */ |
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#define rCMP (0x00) /* Form 1: set <cc> after <roperand1> - <roperand2> */ |
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#define rCMPI (0x10) /* Form 1: set <cc> after <roperand1> - <immediate> */ |
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#define rCMN (0x01) /* Form 1: set <cc> after <roperand1> + <roperand2> */ |
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#define rCMNI (0x11) /* Form 1: set <cc> after <roperand1> + <immediate> */ |
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/* FORM 2: Data movement */ |
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#define rMOV (0x20) /* Form 1: <rdest> = <roperand2> */ |
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#define rMOVI (0x30) /* Form 1: <rdist> = <immediate> */ |
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#define rMVN (0x21) /* Form 1: <rdest> = ~<roperand2> */ |
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#define rMVNI (0x31) /* Form 1: <rdist> = ~<immediate> */ |
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/* FORM 4: Program control */ |
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#define rB (0x40) /* PC += <pcoffset> << 2 */ |
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#define rBEQ (0x41) /* if <cc>->EQ, PC += <pcoffset> << 2 */ |
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#define rBNE (0x42) /* if <cc>->NEQ, PC += <pcoffset> << 2 */ |
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#define rBLT (0x43) /* if <cc>->LT, PC += <pcoffset> << 2 */ |
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#define rBGTE (0x44) /* if <cc>->GTE, PC += <pcoffset> << 2 */ |
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#define rBGT (0x45) /* if <cc>->GT, PC += <pcoffset> << 2 */ |
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#define rBLTE (0x46) /* if <cc>->KTE, PC += <pcoffset> << 2 */ |
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#define rBL (0x47) /* LR=next PC, PC += <pcoffset> << 2 */ |
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/* FORM 3: Arithmetic and logical operations */ |
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#define rADD (0x80) /* Form 3: <rdest> = <roperand1> + <roperand2> */ |
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#define rADDI (0xc0) /* Form 3: <rdest> = <roperand1> + <immediate> */ |
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#define rSUB (0x81) /* Form 3: <rdest> = <roperand1> - <roperand2> */ |
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#define rSUBI (0xc1) /* Form 3: <rdest> = <roperand1> - <immediate> */ |
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#define rRSB (0x82) /* Form 3: <rdest> = -<roperand1> + <roperand2> */ |
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#define rRSBI (0xc2) /* Form 3: <rdest> = -<roperand2> + <immediate> */ |
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#define rMUL (0x83) /* Form 3: <rdest> = <roperand1> * <roperand2> */ |
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#define rMULI (0xc3) /* Form 3: <rdest> = <roperand1> * <immediate> */ |
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#define rDIV (0x84) /* Form 3: <rdest> = <roperand1> / <roperand2> */ |
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#define rDIVI (0xc4) /* Form 3: <rdest> = <roperand1> / <immediate> */ |
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#define rMOD (0x85) /* Form 3: <rdest> = <roperand1> % <roperand2> */ |
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#define rMODI (0xc5) /* Form 3: <rdest> = <roperand1> % <immediate> */ |
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#define rSLL (0x86) /* Form 3: <rdest> = <roperand1> << <roperand2> */ |
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#define rSLLI (0xc6) /* Form 3: <rdest> = <roperand1> << <immediate> */ |
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#define rSRL (0x87) /* Form 3: <rdest> = <roperand1> >> <roperand2> */ |
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#define rSRLI (0xc7) /* Form 3: <rdest> = <roperand1> >> <immediate> */ |
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#define rSRA (0x88) /* Form 3: <rdest> = <roperand1> >> <roperand2> */ |
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#define rSRAI (0xc8) /* Form 3: <rdest> = <roperand1> >> <immediate> */ |
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#define rOR (0x89) /* Form 3: <rdest> = <roperand1> | <roperand2> */ |
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#define rORI (0xc9) /* Form 3: <rdest> = <roperand1> | <immediate> */ |
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#define rAND (0x8a) /* Form 3: <rdest> = <roperand1> & <roperand2> */ |
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#define rANDI (0xca) /* Form 3: <rdest> = <roperand1> & <immediate> */ |
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#define rXOR (0x8b) /* Form 3: <rdest> = <roperand1> xor <roperand2> */ |
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#define rXORI (0xcb) /* Form 3: <rdest> = <roperand1> xor <immediate> */ |
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#define rANDN (0x8c) /* Form 3: <rdest> = <roperand1> & ~<roperand2> */ |
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#define rANDNI (0xcc) /* Form 3: <rdest> = <roperand1> & ~<immediate> */ |
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/* FORM 3: Loads and stores */ |
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#define rLD (0x90) /* Form 3: <rdest> = (<roperand1> + <roperand2>) */ |
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#define rLDI (0xd0) /* Form 3: <rdest> = (<roperand1> + (<immediate> << 2)) */ |
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#define rLDH (0x91) /* Form 3: <rdest> = (<roperand1> + <roperand2>) */ |
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#define rLDIH (0xd1) /* Form 3: <rdest> = (<roperand1> + (<immediate> << 1)) */ |
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#define rLDB (0x92) /* Form 3: <rdest> = (<roperand1> + <roperand2>) */ |
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#define rLDIB (0xd2) /* Form 3: <rdest> = (<roperand1> + <immediate>) */ |
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#define rLDM (0xd3) /* Form 3: Load <immediate> registers. Source |
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* address is roperand1, first dest register is |
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* <rdest>, register count is <immediate> */ |
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#define rST (0x94) /* Form 3: (<roperand1> + <roperand2>) = <rsrc> */ |
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#define rSTI (0xd4) /* Form 3: (<roperand1> + (<immediate> << 2)) = <rsrc> */ |
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#define rSTH (0x95) /* Form 3: (<roperand1> + <roperand2>) = <rsrc> */ |
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#define rSTIH (0xd5) /* Form 3: (<roperand1> + (<immediate> << 1)) = <rsrc> */ |
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#define rSTB (0x96) /* Form 3: (<roperand1> + <roperand2>) = <rsrc> */ |
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#define rSTIB (0xd6) /* Form 3: (<roperand1> + <immediate>) = <rsrc> */ |
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#define rSTM (0xd7) /* Form 3: Store <immediate> registers. Destination |
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* address is roperand1, first source register is |
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* <rsrc>, register count is <immediate> */ |
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#endif /* __RINSN32_H */
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