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396 lines
14 KiB
396 lines
14 KiB
/************************************************************************************ |
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* configs/stm3240g-eval/include/board.h |
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* include/arch/board/board.h |
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* |
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* Copyright (C) 2009 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#ifndef __ARCH_BOARD_BOARD_H |
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#define __ARCH_BOARD_BOARD_H |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include "stm32_rcc.h" |
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#include "stm32_sdio.h" |
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#include "stm32_internal.h" |
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/************************************************************************************ |
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* Definitions |
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************************************************************************************/ |
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/* Clocking *************************************************************************/ |
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/* Four clock sources are available on STM3240G-EVAL evaluation board for |
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* STM32F407IGH6 and RTC embedded: |
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* |
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* X1, 25 MHz crystal for ethernet PHY with socket. It can be removed when clock is |
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* provided by MCO pin of the MCU |
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* X2, 26 MHz crystal for USB OTG HS PHY |
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* X3, 32 kHz crystal for embedded RTC |
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* X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller (It can be removed |
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* from socket when internal RC clock is used.) |
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* |
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* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c: |
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* System Clock source : PLL (HSE) |
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration |
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) |
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) |
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) |
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) |
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* HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) |
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* PLLM : 25 (STM32_PLLCFG_PLLM) |
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* PLLN : 336 (STM32_PLLCFG_PLLN) |
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* PLLP : 2 (STM32_PLLCFG_PLLP) |
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* PLLQ : 7 (STM32_PLLCFG_PPQ) |
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK |
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* Flash Latency(WS) : 5 |
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* Prefetch Buffer : OFF |
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* Instruction cache : ON |
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* Data cache : ON |
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* Require 48MHz for USB OTG FS, : Enabled |
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* SDIO and RNG clock |
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*/ |
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/* HSI - 16 MHz RC factory-trimmed |
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* LSI - 32 KHz RC |
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* HSE - On-board crystal frequency is 25MHz |
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* LSE - 32.768 kHz |
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*/ |
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#define STM32_BOARD_XTAL 25000000ul |
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#define STM32_HSI_FREQUENCY 16000000ul |
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#define STM32_LSI_FREQUENCY 32000 |
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL |
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#define STM32_LSE_FREQUENCY 32768 |
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/* Main PLL Configuration. |
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* |
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* PLL source is HSE |
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN |
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* = (25,000,000 / 25) * 336 |
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* = 336,000,000 |
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* SYSCLK = PLL_VCO / PLLP |
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* = 336,000,000 / 2 = 168,000,000 |
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* USB OTG FS, SDIO and RNG Clock |
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* = PLL_VCO / PLLQ |
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* = 48,000,000 |
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*/ |
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) |
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) |
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 |
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#define STM32_PLLCFG_PPQ RCC_PLLCFG_PLLQ(7) |
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#define STM32_SYSCLK_FREQUENCY 168000000ul |
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/* AHB clock (HCLK) is SYSCLK (168MHz) */ |
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ |
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY |
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ |
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ |
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ |
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) |
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/* Timers driven from APB1 will be twice PCLK1 */ |
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ |
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ |
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* Timers driven from APB2 will be twice PCLK2 */ |
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx |
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* otherwise frequency is 2xAPBx. |
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* Note: TIM1,8 are on APB2, others on APB1 |
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*/ |
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#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY |
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#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY |
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled |
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* in order to avoid RX overrun/TX underrun errors due to delayed responses |
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* to service FIFOs in interrupt driven mode. These values have not been |
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* tuned!!! |
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* |
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* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz |
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*/ |
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) |
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz |
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz |
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*/ |
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#ifdef CONFIG_SDIO_DMA |
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz |
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz |
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*/ |
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#ifdef CONFIG_SDIO_DMA |
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* Ethernet *************************************************************************/ |
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/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ |
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#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) |
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# if !defined(CONFIG_STM32_MII) |
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# warning "CONFIG_STM32_MII required for Ethernet" |
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# elif !defined(CONFIG_STM32_MII_MCO1) |
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# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" |
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# else |
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/* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ |
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# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE |
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# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE |
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# endif |
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#endif |
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/* LED definitions ******************************************************************/ |
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/* The STM3240G-EVAL board has 4 LEDs that we will encode as: */ |
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#define LED_STARTED 0 /* LED1 */ |
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#define LED_HEAPALLOCATE 1 /* LED2 */ |
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#define LED_IRQSENABLED 2 /* LED1 + LED2 */ |
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#define LED_STACKCREATED 3 /* LED3 */ |
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#define LED_INIRQ 4 /* LED1 + LED3 */ |
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#define LED_SIGNAL 5 /* LED2 + LED3 */ |
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#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ |
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#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ |
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/* Button definitions ***************************************************************/ |
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/* The STM3240G-EVAL supports three buttons: */ |
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#define BUTTON_WAKEUP 0 |
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#define BUTTON_TAMPER 1 |
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#define BUTTON_USER 2 |
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#define NUM_BUTTONS 3 |
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#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) |
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#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) |
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#define BUTTON_USER_BIT (1 << BUTTON_USER) |
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/* Alternate function pin selections ************************************************/ |
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/* UART3: |
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* |
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* - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) |
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* - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX |
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*/ |
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#define GPIO_USART3_RX GPIO_USART3_RX_2 |
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#define GPIO_USART3_TX GPIO_USART3_TX_2 |
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/* Ethernet: |
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* |
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* - PA2 is ETH_MDIO |
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* - PC1 is ETH_MDC |
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* - PB5 is ETH_PPS_OUT |
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* - PH2 is ETH_MII_CRS |
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* - PH3 is ETH_MII_COL |
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* - PI10 is ETH_MII_RX_ER |
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* - PH6 is ETH_MII_RXD2 |
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* - PH7 is ETH_MII_RXD3 |
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* - PC3 is ETH_MII_TX_CLK |
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* - PC2 is ETH_MII_TXD2 |
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* - PB8 is ETH_MII_TXD3 |
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* - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK |
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* - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV |
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* - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 |
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* - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 |
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* - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN |
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* - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 |
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* - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 |
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*/ |
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#define GPIO_ETH_PPS_OUT GPIO_ETH_PPS_OUT_1 |
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#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_2 |
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#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_2 |
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#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_2 |
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#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_2 |
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#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_2 |
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#define GPIO_ETH_MII_TXD3 GPIO_ETH_MII_TXD3_1 |
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#define GPIO_ETH_MII_TX_EN GPIO_ETH_MII_TX_EN_2 |
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#define GPIO_ETH_MII_TXD0 GPIO_ETH_MII_TXD0_2 |
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#define GPIO_ETH_MII_TXD1 GPIO_ETH_MII_TXD1_2 |
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#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2 |
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 |
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2 |
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/* PWM |
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* |
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* The STM3240G-Eval has no real on-board PWM devices, but the board can be |
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* configured to output a pulse train using TIM4 CH2. This pin is used by FSMC is |
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* but is also connected to the Motor Control Connector (CN5) just for this |
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* purpose: |
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* |
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* PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB) |
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* |
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* FSMC must be disabled in this case! PD13 is available at: |
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* |
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* Daughterboard Extension Connector, CN3, pin 32 - available |
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* TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD. |
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* Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14. |
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*/ |
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#define GPIO_TIM4_CH2 GPIO_TIM4_CH2_2 |
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/* CAN |
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* |
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* Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2. |
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* |
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* JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver |
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* JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver |
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* |
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* CAN signals are then available on CN10 pins: |
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* |
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* CN10 Pin 7 = CANH |
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* CN10 Pin 2 = CANL |
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* |
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* Mapping to STM32 GPIO pins: |
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* |
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* PD0 = FSMC_D2 & CAN1_RX |
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* PD1 = FSMC_D3 & CAN1_TX |
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* PB13 = ULPI_D6 & CAN2_TX |
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* PB5 = ULPI_D7 & CAN2_RX |
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*/ |
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3 |
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3 |
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#define GPIO_CAN2_RX GPIO_CAN2_RX_2 |
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#define GPIO_CAN2_TX GPIO_CAN2_TX_1 |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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#undef EXTERN |
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#if defined(__cplusplus) |
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#define EXTERN extern "C" |
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extern "C" { |
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#else |
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#define EXTERN extern |
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#endif |
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/************************************************************************************ |
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* Public Function Prototypes |
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************************************************************************************/ |
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/************************************************************************************ |
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* Name: stm32_boardinitialize |
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* |
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* Description: |
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* All STM32 architectures must provide the following entry point. This entry point |
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* is called early in the intitialization -- after all memory has been configured |
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* and mapped but before any devices have been initialized. |
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* |
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************************************************************************************/ |
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EXTERN void stm32_boardinitialize(void); |
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/************************************************************************************ |
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* Button support. |
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* |
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* Description: |
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* up_buttoninit() must be called to initialize button resources. After |
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* that, up_buttons() may be called to collect the current state of all |
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* buttons or up_irqbutton() may be called to register button interrupt |
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* handlers. |
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* |
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* After up_buttoninit() has been called, up_buttons() may be called to |
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* collect the state of all buttons. up_buttons() returns an 8-bit bit set |
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* with each bit associated with a button. See the BUTTON_*_BIT |
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* definitions in board.h for the meaning of each bit. |
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* |
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* up_irqbutton() may be called to register an interrupt handler that will |
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* be called when a button is depressed or released. The ID value is a |
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* button enumeration value that uniquely identifies a button resource. See the |
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* BUTTON_* definitions in board.h for the meaning of enumeration |
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* value. The previous interrupt handler address is returned (so that it may |
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* restored, if so desired). |
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* |
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************************************************************************************/ |
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#ifdef CONFIG_ARCH_BUTTONS |
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EXTERN void up_buttoninit(void); |
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EXTERN uint8_t up_buttons(void); |
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#ifdef CONFIG_ARCH_IRQBUTTONS |
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EXTERN xcpt_t up_irqbutton(int id, xcpt_t irqhandler); |
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#endif |
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#endif |
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#undef EXTERN |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __ARCH_BOARD_BOARD_H */
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