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67 lines
1.6 KiB
67 lines
1.6 KiB
#ifndef _CALYPSO_CLK_H |
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#define _CALYPSO_CLK_H |
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#include <stdint.h> |
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#define CALYPSO_PLL26_52_MHZ ((2 << 8) | 0) |
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#define CALYPSO_PLL26_86_7_MHZ ((10 << 8) | 2) |
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#define CALYPSO_PLL26_87_MHZ ((3 << 8) | 0) |
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#define CALYPSO_PLL13_104_MHZ ((8 << 8) | 0) |
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enum mclk_div { |
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_ARM_MCLK_DIV_1 = 0, |
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ARM_MCLK_DIV_1 = 1, |
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ARM_MCLK_DIV_2 = 2, |
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ARM_MCLK_DIV_3 = 3, |
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ARM_MCLK_DIV_4 = 4, |
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ARM_MCLK_DIV_5 = 5, |
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ARM_MCLK_DIV_6 = 6, |
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ARM_MCLK_DIV_7 = 7, |
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ARM_MCLK_DIV_1_5 = 0x80 | 1, |
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ARM_MCLK_DIV_2_5 = 0x80 | 2, |
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}; |
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void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div); |
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void calypso_pll_set(uint16_t inp); |
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void calypso_clk_dump(void); |
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/* CNTL_RST */ |
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enum calypso_rst { |
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RESET_DSP = (1 << 1), |
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RESET_EXT = (1 << 2), |
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RESET_WDOG = (1 << 3), |
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}; |
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void calypso_reset_set(enum calypso_rst calypso_rst, int active); |
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int calypso_reset_get(enum calypso_rst); |
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enum calypso_bank { |
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CALYPSO_nCS0 = 0, |
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CALYPSO_nCS1 = 2, |
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CALYPSO_nCS2 = 4, |
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CALYPSO_nCS3 = 6, |
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CALYPSO_nCS7 = 8, |
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CALYPSO_CS4 = 0xa, |
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CALYPSO_nCS6 = 0xc, |
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}; |
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enum calypso_mem_width { |
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CALYPSO_MEM_8bit = 0, |
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CALYPSO_MEM_16bit = 1, |
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CALYPSO_MEM_32bit = 2, |
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}; |
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void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws, |
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enum calypso_mem_width width, int we); |
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/* Enable or disable the internal bootrom mapped to 0x0000'0000 */ |
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void calypso_bootrom(int enable); |
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/* Enable or disable the debug unit */ |
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void calypso_debugunit(int enable); |
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/* configure the RHEA bus bridge[s] */ |
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void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout, |
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uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1); |
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#endif /* _CALYPSO_CLK_H */
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