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/************************************************************************************ |
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* nuttx-configs/px4fmu-v2/include/board.h |
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* include/arch/board/board.h |
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* |
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* Copyright (C) 2009 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#ifndef __ARCH_BOARD_BOARD_H |
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#define __ARCH_BOARD_BOARD_H |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include <stm32.h> |
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/************************************************************************************ |
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* Definitions |
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************************************************************************************/ |
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/* Clocking *************************************************************************/ |
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/* The PX4FMUV2 uses a 24MHz crystal connected to the HSE. |
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* |
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* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c: |
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* System Clock source : PLL (HSE) |
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration |
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) |
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) |
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) |
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) |
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* HSE Frequency(Hz) : 24000000 (STM32_BOARD_XTAL) |
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* PLLM : 24 (STM32_PLLCFG_PLLM) |
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* PLLN : 336 (STM32_PLLCFG_PLLN) |
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* PLLP : 2 (STM32_PLLCFG_PLLP) |
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* PLLQ : 7 (STM32_PLLCFG_PPQ) |
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK |
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* Flash Latency(WS) : 5 |
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* Prefetch Buffer : OFF |
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* Instruction cache : ON |
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* Data cache : ON |
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* Require 48MHz for USB OTG FS, : Enabled |
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* SDIO and RNG clock |
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*/ |
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/* HSI - 16 MHz RC factory-trimmed |
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* LSI - 32 KHz RC |
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* HSE - On-board crystal frequency is 24MHz |
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* LSE - not installed |
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*/ |
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#define STM32_BOARD_XTAL 24000000ul |
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#define STM32_HSI_FREQUENCY 16000000ul |
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#define STM32_LSI_FREQUENCY 32000 |
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL |
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//#define STM32_LSE_FREQUENCY 32768 |
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/* Main PLL Configuration. |
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* |
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* PLL source is HSE |
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN |
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* = (25,000,000 / 25) * 336 |
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* = 336,000,000 |
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* SYSCLK = PLL_VCO / PLLP |
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* = 336,000,000 / 2 = 168,000,000 |
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* USB OTG FS, SDIO and RNG Clock |
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* = PLL_VCO / PLLQ |
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* = 48,000,000 |
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*/ |
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(24) |
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) |
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 |
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) |
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#define STM32_SYSCLK_FREQUENCY 168000000ul |
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/* AHB clock (HCLK) is SYSCLK (168MHz) */ |
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ |
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY |
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ |
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ |
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ |
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) |
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/* Timers driven from APB1 will be twice PCLK1 */ |
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ |
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ |
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* Timers driven from APB2 will be twice PCLK2 */ |
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx |
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* otherwise frequency is 2xAPBx. |
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* Note: TIM1,8-11 are on APB2, others on APB1 |
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*/ |
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#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN |
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#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN |
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#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN |
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#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN |
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#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN |
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#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN |
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#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN |
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#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN |
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#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN |
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#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN |
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#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN |
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#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN |
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#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN |
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#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN |
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled |
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* in order to avoid RX overrun/TX underrun errors due to delayed responses |
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* to service FIFOs in interrupt driven mode. These values have not been |
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* tuned!!! |
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* |
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz |
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*/ |
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#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) |
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz |
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz |
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*/ |
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#ifdef CONFIG_SDIO_DMA |
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# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz |
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz |
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*/ |
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#ifdef CONFIG_SDIO_DMA |
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* DMA Channl/Stream Selections *****************************************************/ |
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/* Stream selections are arbitrary for now but might become important in the future |
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* is we set aside more DMA channels/streams. |
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* |
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* SDIO DMA |
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* DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA |
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* DMAMAP_SDIO_2 = Channel 4, Stream 6 |
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*/ |
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#define DMAMAP_SDIO DMAMAP_SDIO_1 |
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/* Alternate function pin selections ************************************************/ |
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/* UARTs */ |
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* Console in from IO */ |
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#define GPIO_USART1_TX 0 /* USART1 is RX-only */ |
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#define GPIO_USART2_RX GPIO_USART2_RX_2 |
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#define GPIO_USART2_TX GPIO_USART2_TX_2 |
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2 |
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#define GPIO_USART2_CTS GPIO_USART2_CTS_2 |
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#define GPIO_USART3_RX GPIO_USART3_RX_3 |
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#define GPIO_USART3_TX GPIO_USART3_TX_3 |
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#define GPIO_USART3_RTS GPIO_USART3_RTS_2 |
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#define GPIO_USART3_CTS GPIO_USART3_CTS_2 |
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#define GPIO_UART4_RX GPIO_UART4_RX_1 |
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#define GPIO_UART4_TX GPIO_UART4_TX_1 |
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#define GPIO_USART6_RX GPIO_USART6_RX_1 |
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#define GPIO_USART6_TX GPIO_USART6_TX_1 |
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#define GPIO_UART7_RX GPIO_UART7_RX_1 |
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#define GPIO_UART7_TX GPIO_UART7_TX_1 |
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/* UART8 has no alternate pin config */ |
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/* UART RX DMA configurations */ |
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#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 |
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 |
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/* CAN |
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* |
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* CAN1 is routed to the onboard transceiver. |
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* CAN2 is routed to the expansion connector. |
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*/ |
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3 |
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3 |
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#define GPIO_CAN2_RX GPIO_CAN2_RX_1 |
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#define GPIO_CAN2_TX GPIO_CAN2_TX_2 |
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/* I2C |
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* |
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* The optional _GPIO configurations allow the I2C driver to manually |
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* reset the bus to clear stuck slaves. They match the pin configuration, |
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* but are normally-high GPIOs. |
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*/ |
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 |
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 |
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#define GPIO_I2C1_SCL_GPIO \ |
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) |
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#define GPIO_I2C1_SDA_GPIO \ |
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) |
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 |
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 |
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#define GPIO_I2C2_SCL_GPIO \ |
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) |
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#define GPIO_I2C2_SDA_GPIO \ |
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) |
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/* SPI |
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* |
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* There are sensors on SPI1, and SPI2 is connected to the FRAM. |
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*/ |
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 |
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 |
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 |
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 |
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 |
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 |
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#define GPIO_SPI4_MISO GPIO_SPI4_MISO_1 |
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#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 |
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#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 |
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/* LED Definitions. Needed if CONFIG_ARCH_LEDs is defined */ |
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#define LED_STARTED 0 |
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#define LED_HEAPALLOCATE 0 |
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#define LED_IRQSENABLED 0 |
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#define LED_STACKCREATED 1 |
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#define LED_INIRQ 1 |
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#define LED_SIGNAL 1 |
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#define LED_ASSERTION 1 |
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#define LED_PANIC 1 |
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/* Board provides GPIO or other Hardware for signaling to timing analyzer */ |
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#if defined(CONFIG_BOARD_USE_PROBES) |
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# define PROBE_N(n) (1<<((n)-1)) |
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# define PROBE_1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14) |
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# define PROBE_2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN13) |
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# define PROBE_3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11) |
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# define PROBE_4 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9) |
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# define PROBE_5 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN13) |
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# define PROBE_6 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN14) |
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# define PROBE_INIT(mask) \ |
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do { \ |
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if ((mask)& PROBE_N(1)) { stm32_configgpio(PROBE_1); } \ |
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if ((mask)& PROBE_N(2)) { stm32_configgpio(PROBE_2); } \ |
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if ((mask)& PROBE_N(3)) { stm32_configgpio(PROBE_3); } \ |
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if ((mask)& PROBE_N(4)) { stm32_configgpio(PROBE_4); } \ |
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if ((mask)& PROBE_N(5)) { stm32_configgpio(PROBE_5); } \ |
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if ((mask)& PROBE_N(6)) { stm32_configgpio(PROBE_6); } \ |
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} while(0) |
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# define PROBE(n,s) do {stm32_gpiowrite(PROBE_##n,(s));}while(0) |
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# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true) |
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#else |
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# define PROBE_INIT(mask) |
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# define PROBE(n,s) |
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# define PROBE_MARK(n) |
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#endif |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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#undef EXTERN |
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#if defined(__cplusplus) |
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#define EXTERN extern "C" |
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extern "C" { |
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#else |
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#define EXTERN extern |
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#endif |
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/************************************************************************************ |
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* Public Function Prototypes |
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************************************************************************************/ |
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/************************************************************************************ |
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* Name: stm32_boardinitialize |
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* |
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* Description: |
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* All STM32 architectures must provide the following entry point. This entry point |
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* is called early in the initialization -- after all memory has been configured |
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* and mapped but before any devices have been initialized. |
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* |
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************************************************************************************/ |
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EXTERN void stm32_boardinitialize(void); |
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#undef EXTERN |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __ARCH_BOARD_BOARD_H */
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