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275 lines
9.1 KiB
275 lines
9.1 KiB
/**************************************************************************** |
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* scripts/script.ld |
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* |
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* Copyright (C) 2016, 2019, 2020 Gregory Nutt. All rights reserved. |
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* Authors: Gregory Nutt <gnutt@nuttx.org> |
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* Igor Misic <igy1000mb@gmail.com> |
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* |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************/ |
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/* The SP Racing H7 Extreme uses an STM32H750VIT6 has 128Kb of main FLASH memory and |
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128 MB external NAND FLASH memory. |
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* The flash memory is partitioned into a User Flash memory and a System |
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* Flash memory. Each of these memories has two banks: |
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* |
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* 1) User Flash memory: |
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* |
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* Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each |
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* Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each |
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* |
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* 2) System Flash memory: |
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* |
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* Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector |
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* Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector |
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* |
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* 3) User option bytes for user configuration, only in Bank 1. |
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* |
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* In the STM32H743II, two different boot spaces can be selected through |
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* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and |
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* BOOT_ADD1 option bytes: |
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* |
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* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. |
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* ST programmed value: Flash memory at 0x0800:0000 |
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* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. |
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* ST programmed value: System bootloader at 0x1FF0:0000 |
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* |
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* The SP Racing H7 Extreme has a Swtich on board, the BOOT0 pin is at ground so by default, |
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* the STM32 will boot to address 0x0800:0000 in FLASH unless the swiutch is |
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* drepresed, then the boot will be from 0x1FF0:0000 |
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* |
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* The STM32H743ZI also has 1024Kb of data SRAM. |
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* SRAM is split up into several blocks and into three power domains: |
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* |
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* 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with |
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* 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus |
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* |
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* 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000 |
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* |
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* The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit |
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* DTCM ports. The DTCM-RAM could be used for critical real-time |
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* data, such as interrupt service routines or stack / heap memory. |
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* Both DTCM-RAMs can be used in parallel (for load/store operations) |
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* thanks to the Cortex-M7 dual issue capability. |
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* |
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* 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000 |
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* |
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* This RAM is connected to ITCM 64-bit interface designed for |
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* execution of critical real-times routines by the CPU. |
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* |
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* 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA |
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* through D1 domain AXI bus matrix |
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* |
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* 2.1) 512Kb of SRAM beginning at address 0x2400:0000 |
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* |
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* 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA |
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* through D2 domain AHB bus matrix |
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* |
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* 3.1) 128Kb of sram beginning at address 0x3000:0000 |
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* 3.2) 128Kb of SRAM2 beginning at address 0x3002:0000 |
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* 3.3) 32Kb of SRAM3 beginning at address 0x3004:0000 |
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* |
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* sram - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000 |
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* |
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* 4) AHB SRAM (D3 domain) accessible by most of system masters |
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* through D3 domain AHB bus matrix |
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* |
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* 4.1) 64Kb of SRAM4 beginning at address 0x3800:0000 |
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* 4.1) 4Kb of backup RAM beginning at address 0x3880:0000 |
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* |
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* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 |
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* where the code expects to begin execution by jumping to the entry point in |
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* the 0x0800:0000 address range. |
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*/ |
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MEMORY |
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{ |
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dtcm (xrw) : ORIGIN = 0x20000000, LENGTH = 128K |
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sram (xrw) : ORIGIN = 0x24000000, LENGTH = 512K |
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sram2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K |
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sram3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K |
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itcm (xrw) : ORIGIN = 0x00000000, LENGTH = 64K |
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flash (xrw) : ORIGIN = 0x08000000, LENGTH = 128K |
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qspi (xrw) : ORIGIN = 0x90100000, LENGTH = 1536K /* FW that run in memory-mapped mode */ |
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qspi2 (xrw) : ORIGIN = 0x90280000, LENGTH = 512K /* FW segment that will be copied to ram and itcm */ |
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conf (xrw) : ORIGIN = 0x90f80000, LENGTH = 64K /* PX4 Config on an single 64kb erasable block. */ |
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} |
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OUTPUT_ARCH(arm) |
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EXTERN(_vectors) |
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ENTRY(_stext) |
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/* |
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* Ensure that abort() is present in the final object. The exception handling |
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* code pulled in by libgcc.a requires it (and that code cannot be easily avoided). |
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*/ |
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EXTERN(abort) |
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EXTERN(_bootdelay_signature) |
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SECTIONS |
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{ |
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.itcm_code : { |
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_start_itcm = ABSOLUTE(.); |
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. = ALIGN(4); |
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*modules__mc_att_control.a:*(.text* .rodata*) |
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*modules__mc_rate_control.a:*(.text* .rodata*) |
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*modules__rc_update.a:*(.text* .rodata*) |
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*drivers__mpu6000.a:*(.text* .rodata*) |
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*drivers__imu__invensense__icm20602.a:*(.text* .rodata*) |
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*drivers__device.a:*(.text* .rodata*) |
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*drivers__pwm_out.a:*(.text* .rodata*) |
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*vehicle_acceleration.a:*(.text* .rodata*) |
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*vehicle_angular_velocity.a:*(.text* .rodata*) |
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*modules__attitude_estimator_q.a:*(.text* .rodata*) |
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*stm32_spi.o(.text* .rodata*) |
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*stm32_dma.o(.text* .rodata*) |
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_end_itcm = ABSOLUTE(.); |
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} > itcm AT > qspi2 |
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_load_itcm = LOADADDR(.itcm_code); |
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.sram_code : { |
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_start_sram = ABSOLUTE(.); |
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. = ALIGN(4); |
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*drivers__dshot.a:*(.text* .rodata*) |
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*modules__mc_pos_control.a:*(.text* .rodata*) |
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*modules__mc_hover_thrust_estimator.a:*(.text* .rodata*) |
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*modules__sensors.a:*(.text* .rodata*) |
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*libc.a:*(.text* .rodata*) |
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*modules__commander.a:*(.text* .rodata*) |
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*modules__dataman.a:*(.text* .rodata*) |
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*modules__events.a:*(.text* .rodata*) |
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*modules__load_mon.a:*(.text* .rodata*) |
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*modules__logger.a:*(.text* .rodata*) |
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*battery_status.a:*(.text* .rodata*) |
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*land_detector.a:*(.text* .rodata*) |
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*uorb_msgs.a:*(.text* .rodata*) |
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*arch_spi.a:*(.text* .rodata*) |
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_end_sram = ABSOLUTE(.); |
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} > sram AT > qspi2 |
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_load_sram = LOADADDR(.sram_code); |
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.text : { |
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_stext = ABSOLUTE(.); |
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*(.vectors) |
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. = ALIGN(32); |
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/* |
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This signature provides the bootloader with a way to delay booting |
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*/ |
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_bootdelay_signature = ABSOLUTE(.); |
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FILL(0xffecc2925d7d05c5) |
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. += 8; |
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*(.text .text.*) |
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*(.rodata .rodata.*) |
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*(.fixup) |
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*(.gnu.warning) |
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*(.gnu.linkonce.t.*) |
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*(.glue_7) |
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*(.glue_7t) |
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*(.got) |
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*(.gcc_except_table) |
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*(.gnu.linkonce.r.*) |
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_etext = ABSOLUTE(.); |
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} > qspi |
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.ramfunc : { |
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_sramfuncs = ABSOLUTE(.); |
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. = ALIGN(4); |
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*(.ramfunc .ramfunc.*) |
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_eramfuncs = ABSOLUTE(.); |
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} > sram AT > qspi |
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_framfuncs = LOADADDR(.ramfunc); |
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/* |
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* Init functions (static constructors and the like) |
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*/ |
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.init_section : { |
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_sinit = ABSOLUTE(.); |
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KEEP(*(.init_array .init_array.*)) |
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_einit = ABSOLUTE(.); |
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} > qspi |
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/* |
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* Construction data for parameters. |
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*/ |
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__param ALIGN(4): { |
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__param_start = ABSOLUTE(.); |
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KEEP(*(__param*)) |
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__param_end = ABSOLUTE(.); |
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} > qspi |
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.ARM.extab : { |
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*(.ARM.extab*) |
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} > qspi |
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__exidx_start = ABSOLUTE(.); |
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.ARM.exidx : { |
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*(.ARM.exidx*) |
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} > qspi |
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__exidx_end = ABSOLUTE(.); |
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_eronly = ABSOLUTE(.); |
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.data : { |
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_sdata = ABSOLUTE(.); |
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*(.data .data.*) |
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*(.gnu.linkonce.d.*) |
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CONSTRUCTORS |
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_edata = ABSOLUTE(.); |
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} > sram AT > qspi |
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.bss : { |
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_sbss = ABSOLUTE(.); |
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*(.bss .bss.*) |
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*(.gnu.linkonce.b.*) |
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*(COMMON) |
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. = ALIGN(4); |
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_ebss = ABSOLUTE(.); |
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} > sram |
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/* Stabs debugging sections. */ |
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.stab 0 : { *(.stab) } |
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.stabstr 0 : { *(.stabstr) } |
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.stab.excl 0 : { *(.stab.excl) } |
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.stab.exclstr 0 : { *(.stab.exclstr) } |
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.stab.index 0 : { *(.stab.index) } |
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.stab.indexstr 0 : { *(.stab.indexstr) } |
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.comment 0 : { *(.comment) } |
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.debug_abbrev 0 : { *(.debug_abbrev) } |
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.debug_info 0 : { *(.debug_info) } |
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.debug_line 0 : { *(.debug_line) } |
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.debug_pubnames 0 : { *(.debug_pubnames) } |
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.debug_aranges 0 : { *(.debug_aranges) } |
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}
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