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56 lines
3.1 KiB
56 lines
3.1 KiB
/**************************************************************************** |
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* |
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* Copyright (c) 2020 PX4 Development Team. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name PX4 nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************/ |
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#pragma once |
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// DMA1 Channel/Stream Selections |
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//--------------------------------------------//---------------------------//---------------- |
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// DMAMAP_USART3_RX // DMA1, Stream 1, Channel 4 |
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// DMAMAP_UART4_RX // DMA1, Stream 2, Channel 4 |
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// DMAMAP_UART7_RX // DMA1, Stream 3, Channel 5 |
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// AVAILABLE // DMA1, Stream 4 |
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// DMAMAP_USART2_RX // DMA1, Stream 5, Channel 4 |
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// DMAMAP_TIM4_UP // DMA1, Stream 6, Channel 2 (DSHOT) |
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// DMA2 Channel/Stream Selections |
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//--------------------------------------------//---------------------------//---------------- |
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#define DMACHAN_SPI4_RX DMAMAP_SPI4_RX_1 // DMA2, Stream 0, Channel 4 (SPI4 sensors RX) |
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 // DMA2, Stream 1, Channel 4 (PX4IO RX) |
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#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3 (SPI1 sensors RX) |
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#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI1 sensors TX) |
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#define DMACHAN_SPI4_TX DMAMAP_SPI4_TX_2 // DMA2, Stream 4, Channel 5 (SPI4 sensors TX) |
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// DMAMAP_TIM1_UP // DMA2, Stream 5, Channel 6 (DSHOT) |
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#define DMAMAP_SDIO DMAMAP_SDIO_2 // DMA2, Stream 6, Channel 4 |
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#define DMAMAP_USART6_TX DMAMAP_USART6_TX_2 // DMA2, Stream 7, Channel 5 (PX4IO TX)
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