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280 lines
12 KiB
280 lines
12 KiB
/************************************************************************************ |
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* nuttx-config/include/board.h |
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* |
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* Copyright (C) 2020 Gregory Nutt. All rights reserved. |
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* Authors: David Sidrane <david.sidrane@nscdg.com> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#pragma once |
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#include "board_dma_map.h" |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include "stm32_rcc.h" |
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#include "stm32_sdmmc.h" |
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/* Clocking *************************************************************************/ |
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/* The board provides the following clock sources: |
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* |
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* X1: 24 MHz crystal for HSE |
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* |
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* So we have these clock source available within the STM32 |
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* |
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* HSI: 16 MHz RC factory-trimmed internal oscillator |
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* HSE: 24 MHz crystal for HSE |
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*/ |
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#define STM32_BOARD_XTAL 24000000ul |
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#define STM32_HSI_FREQUENCY 16000000ul |
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#define STM32_LSI_FREQUENCY 32000 |
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL |
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#define STM32_LSE_FREQUENCY 0 |
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/* Main PLL Configuration. |
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* |
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* PLL source is HSE = 24,000,000 |
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* |
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* PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN |
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* Subject to: |
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* |
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* 1 <= PLLM <= 63 |
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* 4 <= PLLN <= 512 |
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* 150 MHz <= PLL_VCOL <= 420MHz |
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* 192 MHz <= PLL_VCOH <= 836MHz |
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* |
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* SYSCLK = PLL_VCO / PLLP |
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* CPUCLK = SYSCLK / D1CPRE |
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* Subject to |
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* |
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* PLLP1 = {2, 4, 6, 8, ..., 128} |
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* PLLP2,3 = {2, 3, 4, ..., 128} |
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* CPUCLK <= 480 MHz |
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*/ |
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#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE |
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/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR |
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* |
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* PLL1_VCO = (24,000,000 / 2) * 80 = 960 MHz |
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* |
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* PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 480 MHz |
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* PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 240 MHz |
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* PLL1R = PLL1_VCO/8 = 960 MHz / 8 = 120 MHz |
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*/ |
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#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE|RCC_PLLCFGR_PLL1RGE_4_8_MHZ|RCC_PLLCFGR_DIVP1EN|RCC_PLLCFGR_DIVQ1EN|RCC_PLLCFGR_DIVR1EN) |
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#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2) |
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#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(80) |
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#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) |
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#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) |
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#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) |
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#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 80) |
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#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) |
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#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) |
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#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) |
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/* PLL2 */ |
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#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE|RCC_PLLCFGR_PLL2RGE_4_8_MHZ|RCC_PLLCFGR_DIVP2EN|RCC_PLLCFGR_DIVQ2EN|RCC_PLLCFGR_DIVR2EN) |
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#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(4) |
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#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(32) |
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#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(2) |
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#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(2) |
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#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(2) |
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#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 32) |
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#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2) |
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#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 2) |
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#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 2) |
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/* PLL3 */ |
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#define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE|RCC_PLLCFGR_PLL3RGE_4_8_MHZ|RCC_PLLCFGR_DIVQ3EN) |
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#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(4) |
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#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(32) |
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#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2) |
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#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(4) |
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#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(2) |
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#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 32) |
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#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 2) |
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#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 4) |
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#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 2) |
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/* SYSCLK = PLL1P = 480MHz |
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* CPUCLK = SYSCLK / 1 = 480 MHz |
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*/ |
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#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) |
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#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) |
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#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) |
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/* Configure Clock Assignments */ |
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/* AHB clock (HCLK) is SYSCLK/2 (240 MHz max) |
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* HCLK1 = HCLK2 = HCLK3 = HCLK4 = 240 |
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*/ |
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#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ |
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#define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ |
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#define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ |
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ |
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/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */ |
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#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ |
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* APB2 clock (PCLK2) is HCLK/2 (120 MHz) */ |
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#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ |
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* APB3 clock (PCLK3) is HCLK/2 (120 MHz) */ |
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#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 = HCLK / 2 */ |
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#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* APB4 clock (PCLK4) is HCLK/4 (120 MHz) */ |
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#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 = HCLK / 2 */ |
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#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* Timer clock frequencies */ |
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/* Timers driven from APB1 will be twice PCLK1 */ |
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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/* Timers driven from APB2 will be twice PCLK2 */ |
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) |
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/* Kernel Clock Configuration |
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* Note: look at Table 54 in ST Manual |
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*/ |
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#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI /* I2C123 clock source */ |
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#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL2 /* SPI123 clock source */ |
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#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ |
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#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ |
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#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ |
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#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ |
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#define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ |
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#define STM32_FDCANCLK STM32_HSE_FREQUENCY |
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/* FLASH wait states */ |
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#define BOARD_FLASH_WAITSTATES 2 |
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/* SDMMC definitions ********************************************************/ |
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/* Init 400kHz, freq = PLL1Q/(2*div) div = PLL1Q/(2*freq) */ |
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#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) |
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/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div = PLL1Q/(2*freq) |
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* div = 4.8 = 240 / 50, So round up to 5 for default speed 24 MB/s |
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*/ |
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#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA) |
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# define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define STM32_SDMMC_MMCXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) |
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#endif |
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#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA) |
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# define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define STM32_SDMMC_SDXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) |
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#endif |
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#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE |
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/* UART/USART */ |
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#define GPIO_USART1_TX GPIO_USART1_TX_3 /* PB6 */ |
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#define GPIO_USART1_RX GPIO_USART1_RX_3 /* PB7 */ |
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */ |
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#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */ |
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#define GPIO_USART2_CTS GPIO_USART2_CTS_NSS_2 /* PD3 */ |
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2 /* PD4 */ |
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */ |
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */ |
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#define GPIO_USART3_CTS GPIO_USART3_CTS_NSS_2 /* PD11 */ |
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#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ |
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#define GPIO_UART4_TX GPIO_UART4_TX_2 /* PA0 */ |
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#define GPIO_UART4_RX GPIO_UART4_RX_2 /* PA1 */ |
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#define GPIO_USART6_TX 0 /* USART6 is RX-only */ |
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */ |
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#define GPIO_UART7_TX GPIO_UART7_TX_3 /* PE8 */ |
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#define GPIO_UART7_RX GPIO_UART7_RX_3 /* PE7 */ |
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#define GPIO_UART8_TX GPIO_UART8_TX_1 /* PE1 */ |
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#define GPIO_UART8_RX GPIO_UART8_RX_1 /* PE0 */ |
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/* CAN */ |
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3 /* PD0 */ |
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */ |
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#define GPIO_CAN2_RX GPIO_CAN2_RX_1 /* PB12 */ |
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#define GPIO_CAN2_TX GPIO_CAN2_TX_1 /* PB13 */ |
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/* SPI */ |
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#define ADJ_SLEW_RATE(p) (((p) & ~GPIO_SPEED_MASK) | (GPIO_SPEED_2MHz)) |
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#define GPIO_SPI1_SCK ADJ_SLEW_RATE(GPIO_SPI1_SCK_1) /* PA5 */ |
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */ |
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */ |
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#define GPIO_SPI2_SCK ADJ_SLEW_RATE(GPIO_SPI2_SCK_3) /* PB10 */ |
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */ |
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */ |
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#define GPIO_SPI5_SCK ADJ_SLEW_RATE(GPIO_SPI5_SCK_1) /* PF7 */ |
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#define GPIO_SPI5_MISO GPIO_SPI5_MISO_1 /* PF8 */ |
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#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_2 /* PF9 */ |
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#define GPIO_SPI6_SCK ADJ_SLEW_RATE(GPIO_SPI6_SCK_1) /* PG13 */ |
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#define GPIO_SPI6_MISO GPIO_SPI6_MISO_1 /* PG12 */ |
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#define GPIO_SPI6_MOSI GPIO_SPI6_MOSI_1 /* PG14 */ |
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/* I2C */ |
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */ |
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */
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