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139 lines
5.1 KiB
139 lines
5.1 KiB
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_dma.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_dma.c |
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index a695a07..1d54daf 100644 |
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--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_dma.c |
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+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_dma.c |
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@@ -860,6 +860,13 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) |
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* of the processor. Note that this only applies to memory addresses, it |
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* will return false for any peripheral address. |
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* |
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+ * Input Parameters: |
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+ * |
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+ * maddr - starting memory address |
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+ * count - number of unit8 or uint16 or uint32 items as defined by MSIZE of |
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+ * ccr. |
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+ * ccr - DMA stream configuration register |
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+ * |
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* Returned value: |
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* True, if transfer is possible. |
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* |
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@@ -877,7 +884,8 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) |
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* Transfers to/from memory performed by the DMA controller are |
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* required to be aligned to their size. |
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* |
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- * See ST RM0090 rev4, section 9.3.11 |
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+ * See ST RM0410 DocID028270 Rev 2, section 8.3.11 Single and burst |
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+ * transfers |
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* |
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* Compute mend inline to avoid a possible non-constant integer |
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* multiply. |
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@@ -911,6 +919,23 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) |
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return false; |
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} |
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+# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) |
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+ /* buffer alignment is required for DMA transfers with dcache in buffered |
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+ * mode (not write-through) because a) arch_invalidate_dcache could lose |
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+ * buffered writes and b) arch_flush_dcache could corrupt adjacent memory if |
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+ * the maddr and the mend+1, the next next address are not on |
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+ * ARMV7M_DCACHE_LINESIZE boundaries. |
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+ */ |
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+ |
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+ if ((maddr & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || |
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+ ((mend + 1) & (ARMV7M_DCACHE_LINESIZE-1)) != 0) |
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+ { |
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+ dmainfo("stm32_dmacapable: dcache unaligned maddr:0x%08x mend:0x%08x\n", |
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+ maddr, mend); |
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+ return false; |
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+ } |
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+# endif |
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+ |
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/* Verify that burst transfers do not cross a 1KiB boundary. */ |
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if ((maddr / 1024) != (mend / 1024)) |
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diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_dma.h NuttX/nuttx/arch/arm/src/stm32f7/stm32_dma.h |
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index b25cb84..e512b39 100644 |
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--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_dma.h |
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+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_dma.h |
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@@ -241,6 +241,13 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); |
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* only applies to memory addresses, it will return false for any peripheral |
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* address. |
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* |
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+ * Input Parameters: |
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+ * |
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+ * maddr - starting memory address |
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+ * count - number of unit8 or uint16 or uint32 items as defined by MSIZE of |
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+ * ccr. |
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+ * ccr - DMA stream configuration register |
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+ * |
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* Returned value: |
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* True, if transfer is possible. |
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* |
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diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_sdmmc.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_sdmmc.c |
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index 2df98c1..7f81c97 100644 |
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--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_sdmmc.c |
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+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_sdmmc.c |
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@@ -2848,13 +2848,6 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, |
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); |
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- /* Wide bus operation is required for DMA */ |
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- |
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- if (!priv->widebus) |
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- { |
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- return -EINVAL; |
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- } |
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- |
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/* DMA must be possible to the buffer */ |
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if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, |
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@@ -2896,16 +2889,21 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, |
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); |
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#ifdef CONFIG_SDIO_PREFLIGHT |
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DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); |
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-#endif |
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- |
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-#ifdef CONFIG_ARMV7M_DCACHE |
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- /* buffer alignment is required for DMA transfers with dcache */ |
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+#else |
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+# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) |
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+ /* buffer alignment is required for DMA transfers with dcache in buffered |
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+ * mode (not write-through) because the arch_invalidate_dcache could lose |
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+ * buffered buffered writes if the buffer alignment and sizes are not on |
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+ * ARMV7M_DCACHE_LINESIZE boundaries. |
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+ */ |
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if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || |
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(buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0) |
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{ |
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return -EFAULT; |
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} |
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+# endif |
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+ |
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#endif |
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/* Reset the DPSM configuration */ |
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@@ -2981,16 +2979,20 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, |
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); |
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#ifdef CONFIG_SDIO_PREFLIGHT |
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DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); |
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-#endif |
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- |
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-#ifdef CONFIG_ARMV7M_DCACHE |
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- /* buffer alignment is required for DMA transfers with dcache */ |
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+#else |
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+# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) |
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+ /* buffer alignment is required for DMA transfers with dcache in buffered |
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+ * mode (not write-through) because the arch_flush_dcache would corrupt adjacent |
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+ * memory if the buffer alignment and sizes are not on ARMV7M_DCACHE_LINESIZE |
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+ * boundaries. |
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+ */ |
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if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || |
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(buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0) |
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{ |
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return -EFAULT; |
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} |
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+# endif |
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#endif |
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/* Reset the DPSM configuration */
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