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451 lines
18 KiB
451 lines
18 KiB
/************************************************************************************ |
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* configs/fire-stm32v2/include/board.h |
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* include/arch/board/board.h |
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* |
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* Copyright (C) 2012 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#ifndef __CONFIGS_FIRE_STM32V2_INCLUDE_BOARD_H |
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#define __CONFIGS_FIRE_STM32V2_INCLUDE_BOARD_H |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include "stm32_rcc.h" |
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#include "stm32_sdio.h" |
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#include "stm32_internal.h" |
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/************************************************************************************ |
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* Definitions |
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************************************************************************************/ |
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/* Clocking *************************************************************************/ |
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/* HSI - 8 MHz RC factory-trimmed |
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* LSI - 40 KHz RC (30-60KHz, uncalibrated) |
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* HSE - On-board crystal frequency is 8MHz |
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* LSE - 32.768 kHz crytal |
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*/ |
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#define STM32_BOARD_XTAL 8000000ul |
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#define STM32_HSI_FREQUENCY 8000000ul |
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#define STM32_LSI_FREQUENCY 40000 |
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL |
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#define STM32_LSE_FREQUENCY 32768 |
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/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ |
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC |
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#define STM32_CFGR_PLLXTPRE 0 |
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 |
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) |
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/* Use the PLL and set the SYSCLK source to be the PLL */ |
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL |
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL |
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY |
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/* AHB clock (HCLK) is SYSCLK (72MHz) */ |
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK |
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY |
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ |
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/* APB2 clock (PCLK2) is HCLK (72MHz) */ |
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK |
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY |
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ |
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/* APB2 timers 1 and 8 will receive PCLK2. */ |
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) |
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) |
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ |
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 |
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) |
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/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */ |
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) |
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) |
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/* USB divider -- Divide PLL clock by 1.5 */ |
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#define STM32_CFGR_USBPRE 0 |
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx |
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* otherwise frequency is 2xAPBx. |
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* Note: TIM1,8 are on APB2, others on APB1 */ |
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#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY |
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#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY |
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled |
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* in order to avoid RX overrun/TX underrun errors due to delayed responses |
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* to service FIFOs in interrupt driven mode. These values have not been |
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* tuned!!! |
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* |
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* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz |
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*/ |
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) |
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz |
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz |
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*/ |
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#ifdef CONFIG_SDIO_DMA |
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz |
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz |
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*/ |
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#ifdef CONFIG_SDIO_DMA |
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#else |
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# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) |
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#endif |
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/* LED definitions ******************************************************************/ |
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/* The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. These LEDs are not |
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* used by the NuttX port unless CONFIG_ARCH_LEDS is defined. In that case, the |
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* usage by the board port is defined in include/board.h and src/up_autoleds.c. |
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* The LEDs are used to encode OS-related events as follows: |
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*/ |
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/* LED1 LED2 LED3 */ |
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#define LED_STARTED 0 /* OFF OFF OFF */ |
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#define LED_HEAPALLOCATE 1 /* ON OFF OFF */ |
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#define LED_IRQSENABLED 2 /* OFF ON OFF */ |
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#define LED_STACKCREATED 3 /* OFF OFF OFF */ |
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#define LED_INIRQ 4 /* NC NC ON (momentary) */ |
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#define LED_SIGNAL 4 /* NC NC ON (momentary) */ |
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#define LED_ASSERTION 4 /* NC NC ON (momentary) */ |
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#define LED_PANIC 4 /* NC NC ON (2Hz flashing) */ |
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#undef LED_IDLE /* Sleep mode indication not supported */ |
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/* The M3 Wildfire supports several two user buttons: KEY1 and KEY2 */ |
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#define BUTTON_KEY1 0 |
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#define BUTTON_KEY2 1 |
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#define NUM_BUTTONS 2 |
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#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) |
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#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) |
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/* Pin Remapping ********************************************************************/ |
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/* USB 2.0 |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 70 PA11 PA11-USBDM USB2.0 |
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* 71 PA12 PA12-USBDP USB2.0 |
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* 2 PE3 PE3-USB-M USB2.0 |
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*/ |
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/* 2.4" TFT + Touchscreen |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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* 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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* 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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* 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 |
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* 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 |
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* 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen |
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* 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen |
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* 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen |
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* 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen |
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* 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen |
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* 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen |
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* 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen |
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* 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen |
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* 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen |
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* 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen |
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* 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen |
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* 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen |
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* 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset |
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* 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen |
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* 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen |
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* 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen |
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* 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen |
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* 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen |
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* 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen |
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* 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen |
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* 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen |
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* 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen |
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*/ |
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#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) |
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# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" |
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#endif |
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#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) |
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# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" |
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#endif |
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/* AT24C02 |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 |
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* 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 |
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*/ |
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#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) |
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# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" |
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#endif |
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/* Potentiometer/ADC |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 16 PC1 PC1/ADC123-IN11 Potentiometer (R16) |
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* 24 PA1 PC1/ADC123-IN1 |
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*/ |
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/* USARTs |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 68 PA9 PA9-US1-TX MAX3232, DB9 D8, Requires !CONFIG_STM32_USART1_REMAP |
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* 69 PA10 PA10-US1-RX MAX3232, DB9 D8, Requires !CONFIG_STM32_USART1_REMAP |
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* 25 PA2 PA2-US2-TX MAX3232, DB9 D7, Requires !CONFIG_STM32_USART2_REMAP |
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* 26 PA3 PA3-US2-RX MAX3232, DB9 D7, Requires !CONFIG_STM32_USART2_REMAP |
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*/ |
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#if defined(CONFIG_STM32_USART1) && defined(CONFIG_STM32_USART1_REMAP) |
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# errror "USART1 requires CONFIG_STM32_USART1_REMAP=n" |
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#endif |
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#if defined(CONFIG_STM32_USART2) && defined(CONFIG_STM32_USART2_REMAP) |
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# errror "USART2 requires CONFIG_STM32_USART2_REMAP=n" |
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#endif |
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/* 2MBit SPI FLASH |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH |
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* 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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* 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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* 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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*/ |
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#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) |
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# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" |
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#endif |
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/* ENC28J60 |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH |
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* 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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* 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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* 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH |
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* 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset |
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* 4 PE5 (no name) 10Mbps ENC28J60 Interrupt |
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*/ |
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#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) |
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# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" |
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#endif |
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/* MP3 |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 48 PB11 PB11-MP3-RST MP3 |
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* 51 PB12 PB12-SPI2-NSS MP3 |
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* 52 PB13 PB13-SPI2-SCK MP3 |
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* 53 PB14 PB14-SPI2-MISO MP3 |
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* 54 PB15 PB15-SPI2-MOSI MP3 |
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* 63 PC6 PC6-MP3-XDCS MP3 |
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* 64 PC7 PC7-MP3-DREQ MP3 |
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*/ |
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/* SD Card |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 65 PC8 PC8-SDIO-D0 SD card, pulled high |
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* 66 PC9 PC9-SDIO-D1 SD card, pulled high |
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* 78 PC10 PC10-SDIO-D2 SD card, pulled high |
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* 79 PC11 PC10-SDIO-D3 SD card, pulled high |
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* 80 PC12 PC12-SDIO-CLK SD card |
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* 83 PD2 PD2-SDIO-CMD SD card, pulled high |
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*/ |
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/* CAN |
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* |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* PIN NAME SIGNAL NOTES |
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* --- ------ -------------- ------------------------------------------------------------------- |
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* |
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* 95 PB8 PB8-CAN-RX CAN tranceiver, Header 2H |
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* 96 PB9 PB9-CAN-TX CAN tranceiver, Header 2H |
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*/ |
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#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP1) |
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# error "SPI1 requires CONFIG_STM32_CAN1_REMAP1=y" |
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#endif |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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#ifndef __ASSEMBLY__ |
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#undef EXTERN |
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#if defined(__cplusplus) |
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#define EXTERN extern "C" |
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extern "C" { |
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#else |
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#define EXTERN extern |
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#endif |
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/************************************************************************************ |
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* Public Function Prototypes |
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************************************************************************************/ |
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/************************************************************************************ |
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* Name: stm32_boardinitialize |
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* |
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* Description: |
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* All STM32 architectures must provide the following entry point. This entry point |
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* is called early in the intitialization -- after all memory has been configured |
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* and mapped but before any devices have been initialized. |
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* |
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************************************************************************************/ |
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EXTERN void stm32_boardinitialize(void); |
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/************************************************************************************ |
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* Button support. |
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* |
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* Description: |
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* up_buttoninit() must be called to initialize button resources. After |
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* that, up_buttons() may be called to collect the current state of all |
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* buttons or up_irqbutton() may be called to register button interrupt |
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* handlers. |
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* |
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* After up_buttoninit() has been called, up_buttons() may be called to |
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* collect the state of all buttons. up_buttons() returns an 8-bit bit set |
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* with each bit associated with a button. See the BUTTON_*_BIT and JOYSTICK_*_BIT |
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* definitions in board.h for the meaning of each bit. |
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* |
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* up_irqbutton() may be called to register an interrupt handler that will |
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* be called when a button is depressed or released. The ID value is a |
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* button enumeration value that uniquely identifies a button resource. See the |
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* BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of enumeration |
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* value. The previous interrupt handler address is returned (so that it may |
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* restored, if so desired). |
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* |
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************************************************************************************/ |
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#ifdef CONFIG_ARCH_BUTTONS |
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EXTERN void up_buttoninit(void); |
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EXTERN uint8_t up_buttons(void); |
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#ifdef CONFIG_ARCH_IRQBUTTONS |
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EXTERN xcpt_t up_irqbutton(int id, xcpt_t irqhandler); |
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#endif |
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#endif |
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/************************************************************************************ |
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* Name: stm32_ledinit, stm32_setled, and stm32_setleds |
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* |
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* Description: |
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* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If |
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* CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to |
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* control the LEDs from user applications. |
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* |
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************************************************************************************/ |
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#ifndef CONFIG_ARCH_LEDS |
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EXTERN void stm32_ledinit(void); |
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EXTERN void stm32_setled(int led, bool ledon); |
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EXTERN void stm32_setleds(uint8_t ledset); |
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#endif |
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/************************************************************************************ |
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* Name: fire_lcdclear |
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* |
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* Description: |
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* This is a non-standard LCD interface just for the M3 Wildfire board. Because |
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* of the various rotations, clearing the display in the normal way by writing a |
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* sequences of runs that covers the entire display can be very slow. Here the |
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* dispaly is cleared by simply setting all GRAM memory to the specified color. |
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* |
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************************************************************************************/ |
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#ifdef CONFIG_STM32_FSMC |
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EXTERN void fire_lcdclear(uint16_t color); |
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#endif |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __CONFIGS_FIRE_STM32V2_INCLUDE_BOARD_H */
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