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329 lines
11 KiB
329 lines
11 KiB
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c |
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index bd653cf..71adbcf 100644 |
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--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c |
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+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c |
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@@ -1,7 +1,7 @@ |
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/**************************************************************************** |
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* arch/arm/src/stm32f7/stm32_bbsram.c |
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* |
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- * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. |
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+ * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* David Sidrane <david_s5@nscdg.com> |
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* |
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@@ -257,7 +257,7 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv) |
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static inline void stm32_bbsram_unlock(void) |
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{ |
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- (void)stm32_pwr_enablebkp(true); |
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+ stm32_pwr_enablebkp(true); |
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} |
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/**************************************************************************** |
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@@ -277,7 +277,7 @@ static inline void stm32_bbsram_unlock(void) |
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static inline void stm32_bbsram_lock(void) |
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{ |
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- (void)stm32_pwr_enablebkp(false); |
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+ stm32_pwr_enablebkp(false); |
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} |
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/**************************************************************************** |
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diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c |
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index 961eaf4..c9d2d5d 100644 |
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--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c |
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+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c |
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@@ -2,7 +2,7 @@ |
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* arch/arm/src/stm32f7/stm32_pwr.c |
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* |
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* Copyright (C) 2011 Uros Platise. All rights reserved. |
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- * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. |
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+ * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. |
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* Authors: Uros Platise <uros.platise@isotel.eu> |
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* Gregory Nutt <gnutt@nuttx.org> |
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* David Sidrane <david_s5@nscdg.com> |
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@@ -53,6 +53,12 @@ |
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#if defined(CONFIG_STM32F7_PWR) |
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/************************************************************************************ |
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+ * Private Data |
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+ ************************************************************************************/ |
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+ |
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+static uint16_t g_bkp_writable_counter = 0; |
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+ |
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+/************************************************************************************ |
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* Private Functions |
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************************************************************************************/ |
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@@ -76,52 +82,108 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1 |
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************************************************************************************/ |
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/************************************************************************************ |
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+ * Name: stm32_pwr_initbkp |
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+ * |
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+ * Description: |
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+ * Insures the referenced count access to the backup domain (RTC registers, |
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+ * RTC backup data registers and backup SRAM is consistent with the HW state |
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+ * without relying on a variable. |
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+ * |
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+ * NOTE: This function should only be called by SoC Start up code. |
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+ * |
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+ * Input Parameters: |
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+ * writable - True: enable ability to write to backup domain registers |
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+ * |
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+ * Returned Value: |
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+ * None |
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+ * |
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+ ************************************************************************************/ |
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+ |
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+void stm32_pwr_initbkp(bool writable) |
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+{ |
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+ uint16_t regval; |
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+ |
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+ /* Make the HW not writable */ |
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+ |
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+ regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); |
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+ regval &= ~PWR_CR1_DBP; |
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+ stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); |
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+ |
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+ /* Make the reference count agree */ |
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+ |
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+ g_bkp_writable_counter = 0; |
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+ stm32_pwr_enablebkp(writable); |
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+} |
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+ |
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+/************************************************************************************ |
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* Name: stm32_pwr_enablebkp |
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* |
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* Description: |
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* Enables access to the backup domain (RTC registers, RTC backup data registers |
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* and backup SRAM). |
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* |
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+ * NOTE: Reference counting is used in order to supported nested calls to this |
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+ * function. As a consequence, every call to stm32_pwr_enablebkp(true) must |
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+ * be followed by a matching call to stm32_pwr_enablebkp(false). |
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+ * |
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* Input Parameters: |
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* writable - True: enable ability to write to backup domain registers |
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* |
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* Returned Value: |
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- * True: The backup domain was previously writable. |
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+ * None |
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* |
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************************************************************************************/ |
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-bool stm32_pwr_enablebkp(bool writable) |
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+void stm32_pwr_enablebkp(bool writable) |
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{ |
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+ irqstate_t flags; |
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uint16_t regval; |
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bool waswritable; |
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+ bool wait = false; |
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+ |
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+ flags = enter_critical_section(); |
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/* Get the current state of the STM32 PWR control register */ |
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regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); |
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waswritable = ((regval & PWR_CR1_DBP) != 0); |
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+ if (writable) |
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+ { |
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+ DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX); |
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+ g_bkp_writable_counter++; |
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+ } |
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+ else if (g_bkp_writable_counter > 0) |
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+ { |
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+ g_bkp_writable_counter--; |
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+ } |
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/* Enable or disable the ability to write */ |
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- if (waswritable && !writable) |
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+ if (waswritable && g_bkp_writable_counter == 0) |
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{ |
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/* Disable backup domain access */ |
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regval &= ~PWR_CR1_DBP; |
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stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); |
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} |
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- else if (!waswritable && writable) |
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+ else if (!waswritable && g_bkp_writable_counter > 0) |
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{ |
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/* Enable backup domain access */ |
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regval |= PWR_CR1_DBP; |
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stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); |
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+ wait = true; |
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+ } |
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+ |
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+ leave_critical_section(flags); |
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+ |
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+ if (wait) |
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+ { |
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/* Enable does not happen right away */ |
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up_udelay(4); |
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} |
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- |
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- return waswritable; |
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} |
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/************************************************************************************ |
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diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h |
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index 772851d..c80de12 100644 |
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--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h |
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+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h |
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@@ -1,7 +1,7 @@ |
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/************************************************************************************ |
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* arch/arm/src/stm32f7/stm32_pwr.h |
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* |
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- * Copyright (C) 2016 Gregory Nutt. All rights reserved. |
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+ * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. |
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* Authors: Gregory Nutt <gnutt@nuttx.org> |
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* David Sidrane <david_s5@nscdg.com> |
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* |
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@@ -68,6 +68,27 @@ extern "C" |
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************************************************************************************/ |
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/************************************************************************************ |
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+ * Name: stm32_pwr_initbkp |
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+ * |
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+ * Description: |
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+ * Insures the referenced count access to the backup domain (RTC registers, |
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+ * RTC backup data registers and backup SRAM is consistent with the HW state |
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+ * without relying on a variable. |
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+ * |
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+ * NOTE: This function should only be called by SoC Start up code. |
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+ * |
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+ * Input Parameters: |
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+ * writable - set the initial state of the enable and the |
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+ * bkp_writable_counter |
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+ * |
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+ * Returned Value: |
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+ * None |
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+ * |
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+ ************************************************************************************/ |
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+ |
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+void stm32_pwr_initbkp(bool writable); |
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+ |
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+/************************************************************************************ |
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* Name: stm32_pwr_enablebkp |
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* |
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* Description: |
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@@ -78,11 +99,11 @@ extern "C" |
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* writable - True: enable ability to write to backup domain registers |
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* |
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* Returned Value: |
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- * True: The backup domain was previously writeable. |
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+ * none |
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* |
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************************************************************************************/ |
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-bool stm32_pwr_enablebkp(bool writable); |
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+void stm32_pwr_enablebkp(bool writable); |
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/************************************************************************************ |
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* Name: stm32_pwr_enablebreg |
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diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c |
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index 21cac17..a64ce09 100644 |
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--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c |
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+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c |
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@@ -1,7 +1,7 @@ |
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/**************************************************************************** |
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* arch/arm/src/stm32f7/stm32_rcc.c |
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* |
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- * Copyright (C) 2015 Gregory Nutt. All rights reserved. |
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+ * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. |
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* Authors: Gregory Nutt <gnutt@nuttx.org> |
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* David Sidrane <david_s5@nscdg.com> |
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* |
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@@ -52,6 +52,7 @@ |
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#include "chip/stm32_flash.h" |
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#include "stm32_rcc.h" |
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+#include "stm32_pwr.h" |
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/**************************************************************************** |
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* Pre-processor Definitions |
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@@ -113,6 +114,13 @@ void stm32_clockconfig(void) |
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rcc_reset(); |
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+#if defined(CONFIG_STM32F7_PWR) |
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+ |
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+ /* Insure the bkp is initialized */ |
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+ |
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+ stm32_pwr_initbkp(false); |
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+#endif |
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+ |
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#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) |
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/* Invoke Board Custom Clock Configuration */ |
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diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c |
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index bd42b83..5445c01 100644 |
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--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c |
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+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c |
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@@ -1,7 +1,7 @@ |
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/**************************************************************************** |
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* arch/arm/src/stm32f7/stm32_rtc.c |
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* |
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- * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. |
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+ * Copyright (C) 2011, 2015-2017 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* David Sidrane <david_s5@nscdg.com> |
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* |
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@@ -261,7 +261,7 @@ static void rtc_wprunlock(void) |
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* registers and backup SRAM). |
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*/ |
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- (void)stm32_pwr_enablebkp(true); |
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+ stm32_pwr_enablebkp(true); |
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/* The following steps are required to unlock the write protection on all the |
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* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). |
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@@ -300,7 +300,7 @@ static inline void rtc_wprlock(void) |
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* data registers and backup SRAM). |
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*/ |
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- (void)stm32_pwr_enablebkp(false); |
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+ stm32_pwr_enablebkp(false); |
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} |
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/**************************************************************************** |
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@@ -850,7 +850,7 @@ int up_rtc_initialize(void) |
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regval = getreg32(RTC_MAGIC_REG); |
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- (void)stm32_pwr_enablebkp(true); |
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+ stm32_pwr_enablebkp(true); |
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if (regval != RTC_MAGIC) |
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{ |
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@@ -943,7 +943,7 @@ int up_rtc_initialize(void) |
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} |
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} |
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- (void)stm32_pwr_enablebkp(false); |
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+ stm32_pwr_enablebkp(false); |
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/* Loop, attempting to initialize/resume the RTC. This loop is necessary |
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* because it seems that occasionally it takes longer to initialize the |
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@@ -994,7 +994,7 @@ int up_rtc_initialize(void) |
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* backup data registers and backup SRAM). |
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*/ |
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- (void)stm32_pwr_enablebkp(true); |
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+ stm32_pwr_enablebkp(true); |
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/* Remember that the RTC is initialized */ |
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@@ -1014,7 +1014,7 @@ int up_rtc_initialize(void) |
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* data registers and backup SRAM). |
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*/ |
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- (void)stm32_pwr_enablebkp(false); |
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+ stm32_pwr_enablebkp(false); |
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if (ret != OK && nretry > 0) |
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{
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