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533 lines
21 KiB
533 lines
21 KiB
/************************************************************************************ |
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* configs/nxp/fmuk66-e/include/board.h |
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* |
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* Copyright (C) 2016-2018 Gregory Nutt. All rights reserved. |
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* Authors: Gregory Nutt <gnutt@nuttx.org> |
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* Jordan MacIntyre |
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* David Sidrane <david_s5@nscdg.com> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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************************************************************************************/ |
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#ifndef __CONFIG_NXP_FMUK66_V3_INCLUDE_BOARD_H |
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#define __CONFIG_NXP_FMUK66_V3_INCLUDE_BOARD_H |
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/************************************************************************************ |
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* Included Files |
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************************************************************************************/ |
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#include <nuttx/config.h> |
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#ifndef __ASSEMBLY__ |
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# include <stdint.h> |
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#endif |
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#include <arch/chip/chip.h> |
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/************************************************************************************ |
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* Pre-processor Definitions |
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************************************************************************************/ |
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/* |
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* The FMUK66-v3 is populated with a MK66FN2M0VLQ18 has 2 MiB of FLASH and |
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* 256 KiB of SRAM. |
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*/ |
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/* Clocking *************************************************************************/ |
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/* The NXP FMUK66-E uses a 16MHz external powered Oscillator. The Kinetis MCU startup |
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* from an internal digitally-controlled oscillator (DCO). Nuttx will enable the main |
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* external oscillator EXTAL0. The external oscillator can range from |
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* 32.768 KHz up to 50 MHz. The default external source for the MCG oscillator inputs |
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* EXTAL. |
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* |
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* Y1 a High-frequency, Oscillator |
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*/ |
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#define BOARD_EXTAL_LP 1 |
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#define BOARD_EXTAL_FREQ 16000000 /* 16MHz Oscillator Y1 */ |
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#define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator */ |
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#define BOARD_OSC_CR OSC_CR_ERCLKEN /* Enable the OSCERCLK */ |
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#define BOARD_OSC_DIV OSC_DIV_ERPS_DIV1 /* No OSCERCLK Divide */ |
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/* FLL Configuration. |
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* BOARD_EXTAL_FREQ / BOARD_FRDIV has to be in the range 31.25 kHz to 39.0625 |
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* 16 Mhz / MCG_C1_FRDIV_DIV512 = 31.25 kHz * 640 the default for MCG_C4 |
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* FLL is 20Mhz |
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*/ |
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#define BOARD_FRDIV MCG_C1_FRDIV_DIV512 |
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/* PLL Configuration. Either the external clock or crystal frequency is used to |
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* select the PRDIV value. Only reference clock frequencies are supported that will |
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* produce a KINETIS_MCG_PLL_REF_MIN=8MHz >= PLLIN <=KINETIS_MCG_PLL_REF_MAX=16Mhz |
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* reference clock to the PLL. |
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* |
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* PLL Input frequency: PLLIN = REFCLK / PRDIV = 16 MHz / 2 = 8Mhz MHz |
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* PLL Output frequency: PLLOUT = PLLIN * VDIV = 8 MHz * 42 = 336 MHz |
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* MCG Frequency: PLLOUT = 168 Mhz = 336 MHz / KINETIS_MCG_PLL_INTERNAL_DIVBY=2 |
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* |
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* PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE. |
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* VDIV register value is offset by KINETIS_MCG_C6_VDIV_BASE. |
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*/ |
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#define BOARD_PRDIV 2 /* PLL External Reference Divider */ |
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#define BOARD_VDIV 42 /* PLL VCO Divider (frequency multiplier) */ |
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/* Define additional MCG_C2 Setting */ |
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#define BOARD_MCG_C2_FCFTRIM 0 /* Do not enable FCFTRIM */ |
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#define BOARD_MCG_C2_LOCRE0 MCG_C2_LOCRE0 /* Enable reset on loss of clock */ |
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#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV) |
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#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV) |
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#define BOARD_MCG_FREQ (BOARD_PLLOUT_FREQ/KINETIS_MCG_PLL_INTERNAL_DIVBY) |
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/* SIM CLKDIV1 dividers */ |
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#define BOARD_OUTDIV1 1 /* Core = MCG, 168 MHz */ |
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#define BOARD_OUTDIV2 3 /* Bus = MCG / 3, 56 MHz */ |
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#define BOARD_OUTDIV3 3 /* FlexBus = MCG / 3, 56 MHz */ |
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#define BOARD_OUTDIV4 6 /* Flash clock = MCG / 6, 28 MHz */ |
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#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1) |
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#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2) |
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#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) |
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#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) |
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/* Use BOARD_MCG_FREQ as the output SIM_SOPT2 MUX selected by |
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* SIM_SOPT2[PLLFLLSEL] |
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*/ |
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#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK |
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#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ |
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/* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] |
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* SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ] |
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* 48Mhz = 168Mhz X [(1 + 1) / (6 + 1)] |
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* 48Mhz = 168Mhz / (6 + 1) * (1 + 1) |
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*/ |
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#define BOARD_SIM_CLKDIV2_USBFRAC 2 |
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#define BOARD_SIM_CLKDIV2_USBDIV 7 |
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#define BOARD_SIM_CLKDIV2_FREQ (BOARD_SOPT2_FREQ / BOARD_SIM_CLKDIV2_USBDIV * BOARD_SIM_CLKDIV2_USBFRAC) |
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#define BOARD_USB_CLKSRC SIM_SOPT2_USBSRC |
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#define BOARD_USB_FREQ BOARD_SIM_CLKDIV2_FREQ |
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/* Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1)) |
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* SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)] |
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* 84 Mhz = 168 Mhz X [(0 + 1) / (1 + 1)] |
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* 84 Mhz = 168 Mhz / (1 + 1) * (0 + 1) |
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*/ |
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#define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1 |
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#define BOARD_SIM_CLKDIV3_PLLFLLDIV 2 |
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#define BOARD_SIM_CLKDIV3_FREQ (BOARD_SOPT2_FREQ / BOARD_SIM_CLKDIV3_PLLFLLDIV * BOARD_SIM_CLKDIV3_PLLFLLFRAC) |
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#define BOARD_LPUART0_CLKSRC SIM_SOPT2_LPUARTSRC_MCGCLK |
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#define BOARD_LPUART0_FREQ BOARD_SIM_CLKDIV3_FREQ |
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#define BOARD_TPM_CLKSRC SIM_SOPT2_TPMSRC_OCSERCLK |
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#define BOARD_TPM_FREQ BOARD_EXTAL_FREQ |
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/* SDHC clocking ********************************************************************/ |
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/* SDCLK configurations corresponding to various modes of operation. Formula is: |
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* |
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* SDCLK frequency = (base clock) / (prescaler * divisor) |
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* |
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* The SDHC module is always configure configured so that the core clock is the base |
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* clock. Possible values for prescaler and divisor are: |
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* |
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* SDCLKFS: {2, 4, 8, 16, 32, 63, 128, 256} |
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* DVS: {1..16} |
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*/ |
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/* SDHC pull-up resistors **********************************************************/ |
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/* There are external pull-ups on the NXP fmuk66-e |
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* So enable we do not them. |
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*/ |
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#undef BOARD_SDHC_ENABLE_PULLUPS |
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/* Identification mode: Optimal 400KHz, Actual 168Mhz / (32 * 14) = 375 KHz */ |
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#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV32 |
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#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(14) |
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/* MMC normal mode: Optimal 20MHz, Actual 168Mhz / (2 * 5) = 16.8 MHz */ |
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#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 |
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#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(5) |
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/* SD normal mode (1-bit): Optimal 20MHz, Actual 168Mhz / (2 * 5) = 16.8 MHz */ |
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#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 |
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#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(5) |
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/* SD normal mode (4-bit): Optimal 25MHz, Actual Actual 168Mhz / (2 * 4) = 21 MHz (with DMA) |
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* SD normal mode (4-bit): Optimal 20MHz, Actual 168Mhz / (2 * 5) = 16.8 MHz (no DMA) |
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*/ |
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#ifdef CONFIG_KINETIS_SDHC_DMA |
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# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 |
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# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(4) |
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#else |
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# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 |
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# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(5) |
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#endif |
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/* LED definitions ******************************************************************/ |
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/* The NXP FMUK66-E has a separate Red, Green and Blue LEDs driven by the K66 as |
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* follows: |
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* |
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* LED K66 |
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* ------ ------------------------------------------------------- |
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* RED FB_CS0_b/ UART2_CTS_b / ADC0_SE5b / SPI0_SCK / FTM3_CH1/ PTD1 |
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* GREEN FTM2_FLT0/ CMP0_IN3/ FB_AD6 / I2S0_RX_BCLK/ FTM3_CH5/ ADC1_SE5b/ PTC9 |
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* BLUE CMP0_IN2/ FB_AD7 / I2S0_MCLK/ FTM3_CH4/ ADC1_SE4b/ PTC8 |
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* |
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any |
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* way. The following definitions are used to access individual LEDs. |
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*/ |
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/* LED index values for use with board_userled() */ |
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#define BOARD_LED_R 0 |
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#define BOARD_LED_G 1 |
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#define BOARD_LED_B 2 |
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#define BOARD_NLEDS 3 |
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/* LED bits for use with board_userled_all() */ |
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#define BOARD_LED_R_BIT (1 << BOARD_LED_R) |
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#define BOARD_LED_G_BIT (1 << BOARD_LED_G) |
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#define BOARD_LED_B_BIT (1 << BOARD_LED_B) |
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board |
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* the NXP FMUK66-E. The following definitions describe how NuttX controls |
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* the LEDs: |
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* |
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* SYMBOL Meaning LED state |
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* RED GREEN BLUE |
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* ------------------- ---------------------------- ----------------- */ |
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#define LED_STARTED 1 /* NuttX has been started OFF OFF OFF */ |
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#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF OFF ON */ |
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF ON */ |
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON OFF */ |
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#define LED_INIRQ 0 /* In an interrupt (no change) */ |
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#define LED_SIGNAL 0 /* In a signal handler (no change) */ |
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#define LED_ASSERTION 0 /* An assertion failed (no change) */ |
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#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ |
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#undef LED_IDLE /* K66 is in sleep mode (Not used) */ |
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/* Alternative pin resolution *******************************************************/ |
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/* If there are alternative configurations for various pins in the |
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* kinetis_k66pinmux.h header file, those alternative pins will be labeled with a |
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* suffix like _1, _2, etc. The logic in this file must select the correct pin |
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* configuration for the board by defining a pin configuration (with no suffix) that |
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* maps to the correct alternative. |
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*/ |
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/* CAN |
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* Signal Conn Port Pin Name |
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* ------- -------- ----- ----- -------- |
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* CAN0TX P8-2(H) PTB18 97 CAN0_TX |
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* CAN0RX P8-3(L) PTB19 98 CAN0_RX |
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* CAN1TX P19-2(H) PTC16 123 CAN1_TX |
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* CAN1RX P19-3(L) PTC17 124 CAN1_RX |
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* |
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*/ |
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#define PIN_CAN0_RX PIN_CAN0_RX_2 |
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#define PIN_CAN0_TX PIN_CAN0_TX_2 |
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#define PIN_CAN1_RX PIN_CAN1_RX_2 |
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#define PIN_CAN1_TX PIN_CAN1_TX_2 |
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/* 12C |
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* |
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*/ |
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/* I2C0 |
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* |
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* This device can be pinned out to be either or |
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* Bit Pin Device Signal Usage Conn |
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* ----- --- ------- --------------------------- ------ |
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* PTB2 83 I2C0_SCL U_ECH Ultrasonic P13-3 |
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* PTB3 84 I2C0_SDA U_TRI Ultrasonic P13-2 |
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* ----- --- ------- --------------------------- ------ |
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* |
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* Bit Pin Device Signal Usage Conn |
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* ----- --- ------- --------------------------- ------ |
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* PTE24 45 I2C0_SCL IIC_SCL NFC Connector, IIC P2-2 |
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* PTE25 46 I2C0_SDA IIC_SDA NFC Connector, IIC P2-3 |
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* ----- --- ------- --------------------------- ------ |
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*/ |
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#define PIN_I2C0_SCL PIN_I2C0_SCL_4 /* PTE24 IIC_SCL */ |
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#define PIN_I2C0_SDA PIN_I2C0_SDA_4 /* PTE25 IIC_SDA */ |
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/* I2C1 |
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* |
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* Bit Pin Device Signal Usage Conn |
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* ----- --- ------- -------------- ------------- ------ |
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* PTC10 115 I2C1_SCL P_SCL, GPS_SCL Pressure, GPS P3-4 |
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* PTC11 116 I2C1_SDA P_SDA, GPS_SDA Pressure, GPS P3-5 |
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* ----- --- ------- -------------- ------------- ------ |
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*/ |
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#define PIN_I2C1_SCL PIN_I2C1_SCL_1 /* PTC10 GPS / Pressure Sensor*/ |
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#define PIN_I2C1_SDA PIN_I2C1_SDA_1 /* PTC11 GPS / Pressure Sensor */ |
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/* SPI |
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* |
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*/ |
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/* SPI0 FRAM */ |
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#define PIN_SPI0_PCS0 PIN_SPI0_PCS2_1 /* PTC2 SPI_CS FRAM_CS */ |
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#define PIN_SPI0_SCK PIN_SPI0_SCK_2 /* PTC5 SPI_CLK FRAM_SCK */ |
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#define PIN_SPI0_OUT PIN_SPI0_SOUT_2 /* PTC6 SPI_OUT FRAM_MOSI */ |
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#define PIN_SPI0_SIN PIN_SPI0_SIN_2 /* PTC7 SPI_IN FRAM_MISO */ |
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/* SPI1 |
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* FXOS8700CQ Accelerometer |
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* FXAS21002CQ Gyroscope |
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*/ |
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#define PIN_SPI1_PCS0 PIN_SPI1_PCS0_1 /* PTB10 A_CS */ |
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#define PIN_SPI1_PCS1 PIN_SPI1_PCS1_1 /* PTB9 GM_CS */ |
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#define PIN_SPI1_SCK PIN_SPI1_SCK_1 /* PTB11 A_SCLK */ |
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#define PIN_SPI1_OUT PIN_SPI1_SOUT_1 /* PTB16 A_MOSI */ |
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#define PIN_SPI1_SIN PIN_SPI1_SIN_1 /* PTB17 A_MISO */ |
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/* SPI2 |
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* Bit Pin Device Signal Conn |
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* ----- --- ------- --------- ------ |
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* PTB20 99 SPI2_PCS0 SPI2_CS P18-5 |
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* PTB21 100 SPI2_SCK SPI2_CLK P18-2 |
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* PTB22 101 SPI2_SOUT SPI2_OUT P18-3 |
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* PTB23 102 SPI2_SIN SPI2_IN P18-4 |
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* |
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*/ |
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#define PIN_SPI2_PCS0 PIN_SPI2_PCS0_1 /* PTB20 SPI2_CS */ |
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#define PIN_SPI2_SCK PIN_SPI2_SCK_1 /* PTB21 SPI2_CLK */ |
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#define PIN_SPI2_OUT PIN_SPI2_SOUT_1 /* PTB22 SPI2_OUT */ |
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#define PIN_SPI2_SIN PIN_SPI2_SIN_1 /* PTB23 SPI2_IN */ |
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/* UART |
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* |
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* NuttX Will use LPUART0 as the Console |
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* |
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* LPUAR0 |
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* P16 Pin Name K66 Name |
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* -------- ------------ ------ --------- |
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* 2 UART_TX PTD9 LPUART0_TX |
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* 3 UART_RX PTD8 LPUART0_RX |
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* -------- ----- ------ --------- |
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*/ |
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#define PIN_LPUART0_RX (PIN_LPUART0_RX_3 | GPIO_PULLUP) |
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#define PIN_LPUART0_TX PIN_LPUART0_TX_3 |
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/* UART0 |
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* |
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* J7 Pin Name K66 Name |
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* -------- ------------ ------- --------- |
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* 2 PTA2 UART0_TX |
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* 3 PTA1 UART0_RX |
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* 4 PTB3 UART0_CTS |
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* 5 PTB2 UART0_RTS |
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* -------- ------------ ------- --------- |
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*/ |
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#define PIN_UART0_RX PIN_UART0_RX_1 |
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#define PIN_UART0_TX PIN_UART0_TX_1 |
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#define PIN_UART0_CTS PIN_UART0_CTS_3 |
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#define PIN_UART0_RTS PIN_UART0_RTS_3 |
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/* UART1 |
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* |
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* Pin Name K66 Name |
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* ------------- -------------- ----- --------- |
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* P14-3,P15-2 FrSky_IN_RC_IN PTC3 UART1_RX |
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* P14-2 FrSky_OUT PTC4 UART1_TX |
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* ------------- ------------ ----- --------- |
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*/ |
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#define PIN_UART1_RX PIN_UART1_RX_1 |
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#define PIN_UART1_TX PIN_UART1_TX_1 |
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/* UART2 |
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* No Alternative pins for UART2 |
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* |
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* P7 Pin Name K66 Name |
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* -------- ------------ ------- --------- |
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* 2 GPS_TX PTD3 UART2_TX |
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* 3 GPS_RX PTD2 UART2_RX |
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* -------- ------------ ------- --------- |
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*/ |
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/* UART4 |
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* |
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* P10 Pin Name K66 Name |
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* -------- ------------ ------- --------- |
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* 2 UART4_TX PTC15 UART4_TX |
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* 3 UART4_RX PTC14 UART4_RX |
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* 4 UART4_CTS PTC13 UART4_CTS |
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* 5 UART4_RTS PTE27 UART4_RTS |
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* -------- ------------ ------- --------- |
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*/ |
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#define PIN_UART4_RX PIN_UART4_RX_1 |
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#define PIN_UART4_TX PIN_UART4_TX_1 |
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#define PIN_UART4_RTS PIN_UART4_RTS_2 |
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#define PIN_UART4_CTS PIN_UART4_CTS_1 |
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/* |
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* Ethernet TJA1100 OPEN Alliance BroadR-Reach PHY for Automotive Ethernet |
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* ----------------------------------------------------------------------- |
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* |
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* -------------- ----------------- ----------------------------------------- |
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* TJA1100 Board Signal(s) K66F Pin |
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* Pin Signal Function pinmux Name |
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* --- ---------- ----------------- ------------------------------------------ |
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* 1 MDC RMII0_MDC PTB1/RMII0_MDC PIN_RMII0_MDC |
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* 2 INT RMII0_INT_B, PTA27 PTA27 |
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* 3 nRST ENET_RST PTA28 PTA28 |
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* 4 VDDA(1V8) Cap to GND --- --- |
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* 5 XO 25Mhz OSC --- --- |
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* 6 XI 25Mhz OSC --- --- |
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* 7 VDDA(3V3) E_3V3 --- --- |
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* 8 LED (LED_ENABLE = 1) WAKE (LED_ENABLE = 0) --- |
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* 8 VBAT E_3V3 --- --- |
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* 10 nINH ENET_INH PTA8 PTA8 |
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* 11 VDDA(TX) E_3V3 --- --- |
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* 12 TRX_P ENET_P --- --- |
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* 13 TRX_M ENET_P --- --- |
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* 14 VDDD(3V3) E_3V3 --- --- |
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* 15 GND --- --- --- |
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* 16 VDDD(1V8) Cap to GND --- --- |
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* 17 RXER RMII0_RXER PTA5/RMII0_RXER PIN_RMII0_RXER |
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* 18 CRS_DIV RMII_CRSDV PTA14/RMII0_CRS_DV PIN_RMII0_CRS_DV |
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* 19 TXEN RMII0_TXEN PTA15/RMII0_TXEN PIN_RMII0_TXEN |
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* 20 GND --- --- --- |
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* 21 CONFIG1 ENET_CON1 THIS PIN IS A NO CONNECT |
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* 22 CONFIG0 ENET_CONFIG0 PTA24 PTA24 |
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* 23 RXD1 RMII0_RXD_1 PTA12/RMII0_RXD1 PIN_RMII0_RXD1 |
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* 24 RXD0 RMII0_RXD_0 PTA13/RMII0_RXD0 PIN_RMII0_RXD0 |
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* 25 REF_CLK E_REF_CLK PTE26/ENET_1588_CLKIN PIN_ENET_1588_CLKIN |
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* 26 GND2 --- --- --- |
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* 27 VDD(IO) E_3V3 --- --- |
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* 28 TXC --- --- --- |
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* 29 TXEN RMII_TXEN PTA15/RMII0_TXEN PIN_RMII0_TXEN |
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* 30 TXD3 |
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* 31 TXD2 |
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* 32 TXD1 RMII0_TXD_1 PTA17/RMII0_TXD1 PIN_RMII0_TXD1 |
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* 33 TXD0 RMII0_TXD_0 PTA16/RMII0_TXD0 PIN_RMII0_TXD0 |
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* 34 TXER |
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* 35 EN ENET_EN PTA29 PTA29 |
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* 36 MDIO RMII0_MDIO PTB0/RMII0_MDIO PIN_RMII0_MDIO |
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* --- ---------- ----------------- ------------------------------------ |
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* |
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*/ |
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#define PIN_RMII0_MDIO PIN_RMII0_MDIO_1 |
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#define PIN_RMII0_MDC PIN_RMII0_MDC_1 |
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#define PIN_ENET_PHY_RST (GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO | PIN_PORTA | PIN28) |
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#define PIN_ENET_PHY_EN (GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO | PIN_PORTA | PIN29) |
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|
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/* Board provides GPIO or other Hardware for signaling to timing analyzer */ |
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|
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#if defined(CONFIG_BOARD_USE_PROBES) |
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# define PROBE_N(n) (1<<((n)-1)) |
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# define PROBE_1 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTC | PIN1) |
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# define PROBE_2 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTA | PIN6) |
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# define PROBE_3 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTD | PIN4) |
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# define PROBE_4 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTD | PIN5) |
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# define PROBE_5 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTE | PIN11) |
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# define PROBE_6 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTE | PIN12) |
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|
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# define PROBE_INIT(mask) \ |
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do { \ |
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if ((mask)& PROBE_N(1)) { kinetis_pinconfig(PROBE_1); } \ |
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if ((mask)& PROBE_N(2)) { kinetis_pinconfig(PROBE_2); } \ |
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if ((mask)& PROBE_N(3)) { kinetis_pinconfig(PROBE_3); } \ |
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if ((mask)& PROBE_N(4)) { kinetis_pinconfig(PROBE_4); } \ |
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if ((mask)& PROBE_N(5)) { kinetis_pinconfig(PROBE_5); } \ |
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if ((mask)& PROBE_N(6)) { kinetis_pinconfig(PROBE_6); } \ |
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} while(0) |
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|
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# define PROBE(n,s) do {kinetis_gpiowrite(PROBE_##n,(s));}while(0) |
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# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true) |
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#else |
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# define PROBE_INIT(mask) |
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# define PROBE(n,s) |
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# define PROBE_MARK(n) |
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#endif |
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/************************************************************************************ |
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* Public Data |
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************************************************************************************/ |
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|
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#ifndef __ASSEMBLY__ |
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|
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#undef EXTERN |
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#if defined(__cplusplus) |
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#define EXTERN extern "C" |
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extern "C" |
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{ |
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#else |
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#define EXTERN extern |
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#endif |
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|
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/************************************************************************************ |
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* Public Function Prototypes |
|
************************************************************************************/ |
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|
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/************************************************************************************ |
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* Name: kinetis_boardinitialize |
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* |
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* Description: |
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* All kinetis architectures must provide the following entry point. This entry point |
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* is called early in the intitialization -- after all memory has been configured |
|
* and mapped but before any devices have been initialized. |
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* |
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************************************************************************************/ |
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|
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void kinetis_boardinitialize(void); |
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|
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#undef EXTERN |
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#if defined(__cplusplus) |
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} |
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#endif |
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|
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#endif /* __ASSEMBLY__ */ |
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#endif /* __CONFIG_NXP_FMUK66_V3_INCLUDE_BOARD_H */
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